AR# 45056

LogiCORE IP Serial RapidIO Gen2 v1.2 - Idle_selected signal is Hi-Z in simulation

描述

When I simulateLogiCORE IP Serial RapidIO Gen2 v1.2 example design, the signal "idle_selected" is Hi-Z.

解决方案

This is a known issue that is to be fixed in v1.3 release of the core.

Revision History

1/9/2012- Initial release

AR# 45056
日期 05/19/2012
状态 Archive
Type 已知问题
IP