AR# 4506: 12.1 Timing Analyzer - How to determine if the downstream device will have a hold time violation? (trce -s min)
12.1 Timing Analyzer - How to determine if the downstream device will have a hold time violation? (trce -s min)
I want to generate a report for minimum delays in the area of clock-to-pad delays to determine if the device will meet a downstream hold time requirement.
Timing Analyzer, TRACE, and NETGen can all report minimum delays on a design that has been completely routed. To generate a minimum delay report from within Timing Analyzer after PAR has completed, follow these steps:
Generate a report (i.e., Analyze -> Against Timing Constraints (for builds using version 5.1i or later)).
Select Options -> Speed Grade -> Min, and then click OK.
Verify that the generated report used Speed Grade: -0.
To generate a minimum delay post-layout timing report, use the following TRACE command: trce -s min Verify that the generated report used Speed Grade: -0. To generate a simulation netlist with minimum delays, use the following NETGen command: ngdanno -s min To generate a static timing analysis with minimum delays, use the following trce command: trce -s min NOTE: Minimum timing delays represent speeds that do not accurately reflect typical process delays. To determine if a speeds file has minimum timing values, use the Speedprint command, as described in (Xilinx Answer 6067).