2. 技术支持
  3. AR# 4506: 12.1 Timing Analyzer - How to determine if the downstream device will have a hold time violation? (trce -s min)
  4. AR# 45061: AXI Bridge for PCI Express - Instance names of the transceivers for location constraints

AR# 45061

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AXI Bridge for PCI Express - Instance names of the transceivers for location constraints

描述

This answer recordprovides instance names of important components in the AXI Bridge for PCI Express.

解决方案

The following component names will be listed for Virtex-6 and Spartan-6 devices:

  • Clocking components: MMCM and PLL
  • PCI Express Integrated Blocks
  • Transceivers: GTX and GTP_DUAL

Virtex-6 FPGA

Clocking - MMCM_ADV
"*/pcie_clocking_i/mmcm_adv_i"

PCI Express Integrated Block - PCIE_2_0
"*/pcie_2_0_i/pcie_block_i"

Transceiver - GTXE1
"*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX"
"*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX"

Spartan-6 FPGA

Clocking- PLL_BASE
"*_ep_inst/pll_base_i"

PCI Express Integrated Block- PCIE_A1
"*_ep_inst/PCIE_A1"

Transceiver- GTPA1_DUAL
"*/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i"

Revision History
11/30/2011 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44972 AXI Bridge for PCI Express FAQ N/A N/A
AR# 45061
日期 12/15/2012
状态 Active
Type 综合文章
IP
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