AR# 45123

描述

解决方案

This is a known issue in version 13.3 of the ISE design tools. This value needs to be changed for far end loopback to work properly in an asynchronous interface. 

This setting can be changed using the DRP interface built into the IBERT Core. Click on the "DRP Settings" tab and look for the RXDFELPMRESET_TIME setting. The value should be changed to 0x0F.

This issue only affects the Virtex-7 and Kintex-7 FPGA GTX IBERT Core in the ISE 13.3 tools and is scheduled to be fixed in 13.4.