UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45195

MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions

描述

This Release Note and Known Issues Answer Record is for Memory Interface Generator (MIG) 7 series, first released in ISE Design Suite 14.4 and contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide (XTP025).

Starting with Vivado 2013.1, see (Xilinx Answer 54025) for the MIG 7 Series IP Release Notes and Known Issues.

解决方案

General Information

For a list of supported memory interfaces and features for 7 series FPGAs, see the 7 Series FPGAs Memory Interface Solution Data Sheet (DS176) and 7 Series FPGAs Memory Interface Solution User Guide (UG586) located at:

For a list of supported frequencies for 7 series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the 7 Series Documentation Center. The MIG tool includes the appropriate frequency range for each specific memory interface configuration.

For information regarding MIG cores for other FPGAs, see the IP Release Notes Guide (XTP025) to locate the appropriate MIG Release Notes and Known Issues Answer Record.

For general design and troubleshooting information on MIG, see:

(Xilinx Answer 34243) Xilinx MIG Solution Center
(Xilinx Answer 43879) 7 Series MIG DDR3 - Hardware Debug Guide
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 42944) Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 42946) Design Advisory Master Answer Record for Kintex-7 FPGA
(Xilinx Answer 51456) Design Advisory Master Answer Record for Artix-7 FPGA
(Xilinx Answer 42665) MIG 7 Series - Why does the MIG Example Design fail in BitGen?
(Xilinx Answer 42036) MIG 7 Series- Internal/External Vref Guidelines
(Xilinx Answer 40603) MIG 7 Series DDR3/DDR2 - Clocking Guidelines

New Features

  • ISE Design Suite 14.5 and Vivado 2013.1 design tools support
  • Questa SIM 10.1b support
  • Synplify Pro supported version G-2012.09-SP1
  • Support of LPDDR2 SDRAM Verilog designs
  • System Reset Pin Polarity selection
  • Additional clocks selection for AXI interface designs

Note: All users are required to upgrade to the latest production release of MIG.

List of memory devices supported:

ComponentsRDIMMsUDIMMsSODIMMs
DDR3 SDRAMMT41J128M8XX-125/15EMT9JSF25672PZ-1G6/1G4MT9JSF25672AZ-1G9/1G6/1G1MT8KTF51264HZ-1G9
MT41J64M16XX-125G/15EMT9KSF25672PZ-1G4MT8JTF51264AZ-1G6/1G4MT8JTF12864HZ-1G6/1G4
MT41J256M8XX-107/125/15E/187EMT18JSF25672PDZ-1G6MT8JTF12864AZ-1G6/1G4MT8JTF25664HZ-1G4/1G1
MT41J128M16XX-107G/125/15E/187EMT18JSF51272PDZ-1G4/1G6MT8JTF25664AZ-1G4MT8KTF51264HZ-1G9/1G6
MT41J512M8XX-107/125/15EMT9HTF12872PZ-80EMT8KTF51264AZ-1G6/1G4MT8KTF25664HZ-1G6/1G4
MT41J256M16XX-107/125/15EMT9HTF12872PZ-667MT8KTF25664AZ-1G4/1G6MT8KSF25664HZ-1G4
MT41K256M8XX-125/15EMT9KSF51272PZ-1G4MT9HTF12872AZ-80EMT8KTF12864HZ-1G9
MT41K128M16XX-15EMT9KSF25672AZ-1G6/1G4MT16JTF25664HZ-1G4/1G6
MT41K512M8XX-107/125/15EMT16JTF51264AZ-1G4MT16JTF51264HZ-1G4
MT41K256M16XX-107/125/15EMT18JSF25672AZ-1G4MT8JSF25664HDZ-1G4
MT18JSF51272AZ-1G6MT18KSF1G72HZ-1G6
MT8HTF12864AZ-800MT18KSF51272HZ-1G4
MT8HTF25664AZ-800MT8HTF12864HZ-800
MT8HTF25664HZ-800
MT4KTF25664HZ-1G9
MT8KTF51264HDZ-1G6
DDR3L SDRAMMT41K512M8THD-15E
MT16KTF51264AZ-1G4
MT16KSF51264HZ-1G4
MT41K256M32SLD-125E
MT16KTF51264AZ-1G6
MT16KTF51264HZ-1G4
MT18KSF51272AZ-1G4
MT16KTF51264HZ-1G6
MT4KTF25664HZ-1G9
MT8KTF51264HDZ-1G6
DDR2 SDRAMMT47H128M16XX-25EMT9HTF12872PZ-80EMT8HTF12864AZ-800MT8HTF12864HZ-800
MT47H128M8XX-25/25EMT9HTF12872PZ-667MT8HTF25664AZ-800MT8HTF25664HZ-800
MT47H256M8XX-25EMT18HTF25672PZ-667MT9HTF12872AZ-80E
MT47H64M16XX-25/25E
MT47H512M8WTR-25E
MT47H64M16HR-25E
QDRII+ SRAMK7S3236T4C-FC45
K7S3218T4C-FC45
CY7C15632KV18-500BZC
CY7C1565KV18-500BZC
CY7C25632KV18-500BZC
CY7C2565KV18-500BZC
CY7C2263KV18-550BZXI
CY7C2265KV18-550BZC
CY7C2163KV18-550BZXI
CY7C2165KV18-550BZC
CY7C25632KV18-450BZC
CY7C2565KV18-450BZC
CY7C25442KV18-333BZI*
CY7C2264XV18-450BZXC*
CY7C2262XV18-450BZXC*
CY7C2564XV18-450BZXC*
CY7C2562XV18-450BZXC*
RLDRAM IIMT49H16M36XX-18/25E/25/33
MT49H32M18XX-18/25E/25/33
MT49H8M36XX-25/33
MT49H16M18XX-25/33
RLDRAM IIIMT44K16M36XX-125
MT44K16M36XX-125E
MT44K32M18XX-125
MT44K32M18XX-125E
MT44K32M36XX-125
MT44K32M36XX-125E
*Components for Burst Length 2

Known Issues

This table correlates the core version to the first ISE design tools release version in which it was included.

Core
Version
ISE
Version
Vivado
Version
1.9/1.9a14.52013.1
1.8 / 1.8.a14.42012.4
1.7 / 1.7.a14.32012.3
1.614.22012.2
1.514.12012.1
1.413.4NA
1.313.3NA
1.213.2NA
1.113.1NA



MIG 7 Series DDR3/DDR2 SDRAM

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM. Please see table at the bottom of these release notes for Vivado specific information.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 51687)

Design Advisory MIG 7 Series DDR3/DDR2 - Temperature monitor calibration using XADC block added to all DDR3/DDR2 designs in v1.7 (ISE 14.3/Vivado 2012.3)

NA1.7
(Xilinx Answer 51296)Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases NA1.6
(Xilinx Answer 50086)MIG 7 Series v1.5 DDR3 - Updated Trace Matching Requirement for CK/CK# and DQS/DQS#1.51.6
(Xilinx Answer 46782)MIG 7 Series v1.4 DDR2 SDRAM - "Error:MapLib:1121" occurs when KEEP HIERARCHY is set to "YES"1.41.9
(Xilinx Answer 55011)MIG 7 Series DDR3 - PRBS Read Leveling Debug signals are not connected to dbg_dqs VIO control1.8Not Resolved
(Xilinx Answer 55531)Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied1.9Not Resolved
(Xilinx Answer 55060)MIG 7 Series DDR3/DDR2 - AXI Interface Enabled - Controller services write command before read is completed.1.8Not Resolved
(Xilinx Answer 55056)MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts1.8Not Resolved
(Xilinx Answer 54845)MIG 7 Series - v1.8 - No instantiation template provided for VHDL version of core1.8Not Resolved

MIG 7 Series - DDR3, LPDDR2, and DDR2 support changes for Virtex-7 HT devices1.9N/A
(Xilinx Answer 55013)MIG 7 Series DDR3 - The MIG 7 Series tool does not allow selecting 800 MHz for dual rank DIMMs in a -2 FPGA design when a 1.35V/1.5V part is selected using the 1.5V option1.82.0
(Xilinx Answer 55015)MIG 7 Series DDR3 - dbg_dqs VIO selection is not connected to mux_rd_rise/fall signals in ChipScope ILAs.1.8Not Resolved
(Xilinx Answer 54918)MIG 7 Series DDR3 - ChipScope Debug Signals connections for OCLKDELAY calibration are out of date after installing patch from (Xilinx Answer 53420)1.7Not Resolved
(Xilinx Answer 54710)MIG 7 Series - DDR3 - Controller hangs on a read-modify-write operation1.8Not Resolved
(Xilinx Answer 54673)MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled.1.8Not Resolved
(Xilinx Answer 54384)MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected1.8Not Resolved
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.5Not Resolved
(Xilinx Answer 53299)MIG 7 Series - MIG fails during synthesis if System Clock = No Buffer and Reference Clock = Use System Clock1.81.9
(Xilinx Answer 54262)MIG 7 Series DDR3 - Dual rank example design incorrectly detects data compare error when reading from 2nd rank address space1.81.9
(Xilinx Answer 53249)MIG 7 Series - Clock input must be connected manually with NO BUFFER option when multiple cores are generated. 1.71.9
(Xilinx Answer 53860)Design Advisory for MIG 7 Series DDR3 - All CK clock pins must to be in the same byte lane/group. Validating Dual Rank Pin-Outs Required.1.61.8
(Xilinx Answer 53420)Design Advisory for MIG 7 Series DDR3 - Required calibration patch for v1.7 and v1.81.71.9
(Xilinx Answer 53435) MIG 7 Series DDR3/DDR2 - Timing violations may be seen in 2:1 designs running around 533MHz within u_ddr_mc_phy
1.8Not Resolved
(Xilinx Answer 53433)MIG 7 Series DDR3/DDR2 - MAX_FANOUT attribute not being honored1.8Not Resolved
(Xilinx Answer 53704)MIG 7 Series DDR3 - Incorrect generation of single rank designs that include multiple sets of ODT, CS, and CKE1.81.9
(Xilinx Answer 53910)MIG 7 Series DDR3 - Incorrect maximum frequency in MIG 7 Series tool for MT41K512M8THD-15E dual rank Micron device1.81.9
(Xilinx Answer 53434)MIG 7 Series DDR3 - Potential timing violations in OCLKDELAY calibration1.71.8
(Xilinx Answer 52573)Design Advisory MIG 7 Series DDR3 - Issue with OCLKDELAY calibration causes write DQS to be aligned to DQ with potential calibration failures 1.71.8
(Xilinx Answer 52541)MIG v1.7 DDR3/DDR2 - Increase in simulation time between v1.6 and v1.71.71.8
(Xilinx Answer 52176)MIG 7 Series DDR3 - 48-bit design unable to fit into 2 HP banks1.6Not Resolved
(Xilinx Answer 52147)MIG 7 Series DDR3 - tRFC and tRAS simulation errors occur during calibration when running at or below 400 MHz 1.71.8
(Xilinx Answer 52131)MIG 7 Series DDR3/DDR2 - Setting the Traffic Generator to use the PHY_CALIB data pattern on vio_data_mode_value does not work properly1.71.8
(Xilinx Answer 52124)MIG 7 Series DDR3/DDR2 - Synplify fails due to parameter DQS_BIAS1.71.9
(Xilinx Answer 52123)MIG 7 Series DDR3/DDR2 - Calibration fails during PRBS Read Leveling stage when using a 2:1 core1.71.8
(Xilinx Answer 52122)MIG 7 Series DDR3/DDR2 - DQS_AUTO_RECAL parameter causes error when using Synplify as synthesis tool1.71.9
(Xilinx Answer 52099)MIG 7 Series - Incorrect behavior when using Synplify with a MIG design that uses the I/O Low Power feature. 1.61.9
(Xilinx Answer 51351)MIG 7 Series DDR3/DDR2- "ERROR:HDL Compiler:532 - Index <71> is out of range [63:0] for signals <wr_data_mask data>" occurs when using ECC_TEST="ON" 1.51.9
(Xilinx Answer 52009)MIG 7 Series DDR3/DDR2 - DQS_BIAS is incorrectly reported as "OFF" on the n-side of the DQS IOBUFDS primitive 1.61.7
(Xilinx Answer 51070)MIG 7 Series DDR3L - MIG data rates do not match data rates specified in DS183/DS182 DC and Switching Characteristics 1.51.7
(Xilinx Answer 50698)MIG 7 Series DDR3/DDR2 - some configurations are failing to meet timing do to logic not being placed properly1.51.7
(Xilinx Answer 47389)MIG 7 Series DDR3 - multi-controller designs may fail timing in certain configurations1.51.7
(Xilinx Answer 47372)MIG 7 Series - Designs fail during MAP stage when XST "KEEP_HIERARCHY" option is set to "YES"1.41.7
(Xilinx Answer 50734)MIG 7 Series DDR3 - additional levels of logic may cause certain configurations to fail timing1.61.7
(Xilinx Answer 50704)MIG 7 Series DDR3 - a few DDR3 SDRAM parts support both 1.5V and 1.35V1.61.7
(Xilinx Answer 50702)MIG 7 Series - VHDL designs fail simulation when using ISIM and Vivado Simulator1.61.7
(Xilinx Answer 50461)Design Advisory MIG 7 Series v1.6 - Calibration updates for all interfaces1.51.6
(Xilinx Answer 50746)MIG 7 Series DDR3 - Incorrect CL generated for all Micron -107 speed grade devices1.51.6
(Xilinx Answer 47699)MIG 7-Series - Input clock period set in mig.prj not maintained when generating the design using "Verify Pin Changes and Update Design" 1.51.6
(Xilinx Answer 47929)MIG 7 Series DDR3/DDR2 - When creating a custom memory part, the tREFI parameter does not get generated correctly 1.51.6
(Xilinx Answer 50739)MIG 7 Series - Does MIG allocate memory interface pins on the reserved PUDC_B configuration pin? 1.01.6
(Xilinx Answer 47929)MIG 7 Series DDR3/DDR2 - when creating a custom memory part the tREFI parameter does not get generated correctly1.41.6
(Xilinx Answer 50701)MIG 7 Series DDR3 - MIG incorrectly assigns 2 Chip Select (CS) pins to the single rank part MT9JSF25672PZ1.51.6
(Xilinx Answer 50700)MIG 7 Series DDR3 - DQSFOUND calibration stage can go into infinite loop1.51.6
(Xilinx Answer 50699)MIG 7 Series - VCC_AUX can get set incorrectly in certain multi-controller configurations1.51.6
(Xilinx Answer 50697)MIG 7 Series DDR3 - tRFC maximum violation reported by memory model during DQS FOUND calibration stage1.51.6
(Xilinx Answer 50696)MIG 7 Series - unable to run the memory clock frequency at 533 MHz using a 200 MHz input clock1.41.6
(Xilinx Answer 43344)MIG 7-Series DDR3/DDR2 - Dynamic calibration and periodic read behaviorNANA
(Xilinx Answer 47773)MIG 7 Series DDR3 RDIMM - designs not working in hardware1.51.6
(Xilinx Answer 47389)MIG 7 Series DDR3 - multi-controller designs might fail timing in certain configurations1.51.6
(Xilinx Answer 47108)MIG 7 Series DDR2/DDR3 - Synplify Pro fails when "I/O Power Reduction" is enabled1.51.6
(Xilinx Answer 47247)MIG 7 Series DDR2/DDR3 - multi-cycle XDC constraints incorrectly set when "I/O Power Reduction" is disabled1.51.6
(Xilinx Answer 47259)MIG 7 Series DDR2/DDR3 - VHDL designs fail during simulation using ISIM1.51.6
(Xilinx Answer 47350)MIG 7 Series DDR2/DDR3 - Synplicity fails to compile VHDL designs1.51.6
(Xilinx Answer 47383)MIG 7 Series DDR2/DDR3 (2:1 Mode) - Timing violations on phy_control paths might occur when interface is spread across three banks1.4 1.6
(Xilinx Answer 45937)MIG 7 Series v1.4 DDR3 - Dual Rank Support1.41.6
(Xilinx Answer 47043)MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE design tools version14.1) 1.5NA
(Xilinx Answer 47250)MIG 7 Series v1.5 - After clicking "Cancel", the CORE Generator tool still appears to generate a MIG core.1.51.6
(Xilinx Answer 46866)MIG 7 Series v1.4 DDR2/DDR3 - Traffic generator flags data errors incorrectly1.41.5
(Xilinx Answer 46676)MIG 7 Series v1.4 RLDRAM II - Synthesis fails when DEBUG_PORT is turned OFF in RTL1.41.5
(Xilinx Answer 46487)MIG 7 Series v1.4 DDR3 - 2:1 mode disabled for frequencies below 400 MHz1.41.5
(Xilinx Answer 45633)Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT. Existing UCFs must be verified.1.11.4
(Xilinx Answer 45653)Design Advisory MIG 7 Series v1.4 DDR2/DDR3 - Calibration Update1.41.5
(Xilinx Answer 42832)MIG 7 Series v1.2 DDR3 - FULL calibration mode violates tREFI requirement1.21.5
(Xilinx Answer 45666)MIG 7 Series v1.4 DDR3 - Generate unrouted design for multi-controller design1.41.5
(Xilinx Answer 45717)MIG 7 Series DDR3 - Multi-Controller designs fail to generate in MIG 1.41.5
(Xilinx Answer 45721)MIG 7 Series (all design) - System/Reference Clock pins not selectable in two bank Zynq devicesNANA
(Xilinx Answer 42833)MIG 7 Series v1.2 DDR3 - Parity error for RDIMM designs during memory initialization and calibration process1.21.6
(Xilinx Answer 42831)MIG 7 Series DDR3/QDRII+/RLDRAM II - Design fails in core generation with single-ended system clock 1.21.6
(Xilinx Answer 44854)MIG 7 Series v1.3 DDR3 -Certain configurations cause design to stick in calibration 1.31.4
(Xilinx Answer 44759)MIG 7 Series v1.3 DDR3 - No traffic is generated in hardware when DEBUG is enabled 1.31.4
(Xilinx Answer 44529)MIG 7 Series v1.2 DDR3 - Incorrect MAP parameters when CKE and ODT are allocated to a byte group separate from the remaining address/control signals (ERROR:Route:471) 1.31.4
(Xilinx Answer 44652)MIG 7 Series v1.3 DDR3 - Timing errors on PHYCTLEMPTY path occur at highest supported frequencies 1.31.4
(Xilinx Answer 44540)MIG 7 Series v1.3 DDR3 - The example design does not generate any traffic in hardware when the Debug feature is enabled 1.31.4
(Xilinx Answer 44695)MIG 7 Series v1.3 - sys_rst is not validated properly using the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44356)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation 1.31.4
(Xilinx Answer 44352)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Incorrect pinout is generated in the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44350)MIG 7 Series v1.3 - Does not support -2L speed grade 1.31.4
(Xilinx Answer 44348)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not able to proceed past bank selection or system pins selection page 1.31.4
(Xilinx Answer 44018)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Synplify Pro will not be supported in 13.3 1.31.4
(Xilinx Answer 43481)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules 1.31.4
(Xilinx Answer 43100)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Status signal names have changed to provide uniformity across all interfaces1.31.3
General InfoTRCE timing is not guaranteed for all configurations at high frequencies. This will be fixed in MIG v1.4 to be released with ISE software version13.4. 1.31.4
(Xilinx Answer 50735)MIG 7 Series DDR3/DDR2 - vio_instr_mode_value 0x1 and 0xE do not work properly1.21.6
(Xilinx Answer 43250)MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF constraint is not applied across all memory banks1.21.4
(Xilinx Answer 42678)13.2 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"13.213.4
(Xilinx Answer 42811)MIG 7 Series v1.2 v1.3 - Setup error on PHY hard blocks due to incorrect timing model 1.21.4
General InfoFixed issues with extra UCF constraints generation for DDR3 SDRAM when ddr3_reset_n pin is allocated in a separate bank1.21.3
(Xilinx Answer 42836)MIG 7 Series v1.2 - Incorrect Phaser IN and PHASER OUT constraints generated for compatible Artix-7 device1.21.3
(Xilinx Answer 43908)MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL" option is not documented in UG5861.21.4
(Xilinx Answer 44019)MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation1.21.4
(Xilinx Answer 42808)MIG 7 Series v1.2 - Component switching limit error on PHY hard blocks due to incorrect timing model1.21.3
(Xilinx Answer 44527)MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance1.21.3
(Xilinx Answer 42660)MIG 7 Series v1.2 supports Virtex-7 XT and Artix-7 devices. In the ISE Design Suite 13.2 release, these devices are Limited Access and license controlled. Targeting one of these devices in MAP without the required license will result in security messages.1.21.3
(Xilinx Answer 42559)MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Additional hard block constraints are incorrectly generated when the reset_n pin is moved to a different bank for a multi-controller design.1.11.3
(Xilinx Answer 42036)MIG v1.1-v1.2 DDR3 - Internal/External Vref Guidelines(incorrect frequency limits)1.11.3
(Xilinx Answer 41981)MIG 7 Series v1.1 DDR3 SDRAM - Addr/Cntrl pins should be limited to a single bank1.11.3
(Xilinx Answer 40876)MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications1.11.2
(Xilinx Answer 40426)MIG 7 Series v1.1 - Unrequested Reads are seen in simulation immediately after calibration completes1.11.2
(Xilinx Answer 40452)MIG 7 Series v1.1 - Memory interface should not span both High Range (HR) and High Performance (HP) banks1.11.2
(Xilinx Answer 40453)MIG 7 Series v1.1 - Can clk_ref_i, sys_rst, and status signals be located in memory banks (Data or Address/Control banks)?1.11.2
(Xilinx Answer 41244)MIG 7 Series 1.1 - Selected device is not supported by MIG version 1.11.11.2
(Xilinx Answer 42320)MIG v3.7 Virtex-6 and MIG 7 Series v1.1, DDR3 RDIM - Incorrect Column Address Width1.11.2
General InfoTRCE timing is not guaranteed for all configurations and at high frequencies (above 800 MHz memory clock for DDR3 SDRAM interfaces) 1.11.2
General InfoCreate Custom Part functionality is not supported for EDK designs 1.11.2


MIG 7 Series QDRII+ SRAM

The following table provides known issues for MIG 7 Series QDRII+ SRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 56682)MIG 7 Series QDRII+ - Write Calibration may fail for x18 multiple component designs when K/K# is not located in the same byte lane as write data2.0Not Resolved
(Xilinx Answer 55884)MIG 7 Series QDRII+ - "pi_edge_adv" can be stuck during calibration which may lead to data failures1.9Not Resolved
(Xilinx Answer 55602)MIG 7 Series QDRII+ - data failures can occur when Fixed Latency mode is enabled1.7Not Resolved
(Xilinx Answer 54845)MIG 7 Series - v1.8 - No instantiation template provided for VHDL version of the core1.8Not Resolved
(Xilinx Answer 54942)MIG 7 Series QDRII+ - ADDR_CTL_MAP parameter width incorrect when 4 addr/ctrl bytes used1.8Not Resolved
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8Not Resolved
(Xilinx Answer 53607)Design Advisory for MIG 7 Series QDRII+ - Inferred latches cause write calibration failures. Work-around required.1.71.9
(Xilinx Answer 53375)MIG 7 Series QDRII+ and RLDRAM II/3 - timing paths from PHASER_IN to OSERDES are not analyzed due to missing clock definition1.71.9
(Xilinx Answer 53053)Design Advisory MIG 7 Series QDRII+ - read calibration failures can occur when CPT_CLK_CQ_ONLY=FALSE1.71.8
(Xilinx Answer 53136)MIG 7 Series QDRII+ - a latch is incorrectly inferred when using Synplify and CPT_CLK_CQ_ONLY=TRUE1.71.8
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.5Not Resolved
(Xilinx Answer 55129)MIG 7 Series QDRII+ - Cypress memory model fails simulation for designs with Burst Length(BL) = 2 and Data Width = 181.5Not Resolved
(Xilinx Answer 50753)MIG 7 Series QDRII+ - All Burst Length 2 (BL=2) designs will fail calibration when using ISIM1.5Not Resolved
(Xilinx Answer 50699)MIG 7 Series - VCC_AUX can get set incorrectly in certain multi-controller configurations1.51.6
(Xilinx Answer 50697)MIG 7 Series - unable to run the memory clock frequency at 533 MHz using a 200 MHz input clock1.41.5
(Xilinx Answer 47043)MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE software version14.1)1.5NA
(Xilinx Answer 47372)MIG 7 Series - Designs fail during MAP stage when XST "KEEP_HIERARCHY" option is set to "YES" 1.4 Not Resolved
(Xilinx Answer 46617)MIG 7 Series - QDRII+ design missing PHASER_OUT constraints for Read Data Paths1.41.5
(Xilinx Answer 45764)MIG QDRII+/RLDRAMII - create_ise.bat/.sh fails when Debug Port is disabled 1.41.5
(Xilinx Answer 45447)MIG 7 Series RLDRAM II and QDRII+ - skew on the K/K# clocks can cause calibration failures 1.31.5
(Xilinx Answer 42831)MIG 7 Series DDR3/QDRII+/RLDRAM II - Design fails in core generation with single-ended system clock 1.21.6
(Xilinx Answer 45721)MIG 7 Series (all design) - System/Reference Clock pins not selectable in two bank Zynq devices NANA
(Xilinx Answer 44695)MIG 7 Series v1.3 - sys_rst is not validated properly using the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44356)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation 1.31.4
(Xilinx Answer 44352)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Incorrect pinout is generated in the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44350)MIG 7 Series v1.3 - Does not support -2L speed grade 1.31.4
(Xilinx Answer 44348)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not able to proceed past bank selection or system pins selection page 1.31.4
(Xilinx Answer 44018)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Synplify Pro will not be supported in 13.3 1.31.4
(Xilinx Answer 43481)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules 1.31.4
(Xilinx Answer 43100)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Status signal names have changed to provide uniformity across all interfaces <1.31.3
(Xilinx Answer 42811)MIG 7 Series v1.2 - Setup error on PHY Hard blocks due to incorrect timing model1.21.4
(Xilinx Answer 42808)MIG 7 Series v1.2 - Component switching limit error on PHY hard blocks due to incorrect timing model1.21.3
(Xilinx Answer 42836)MIG 7 Series v1.2 - Incorrect PHASER IN and PHASER OUT constraints generated for compatible Artix-7 device1.21.3
(Xilinx Answer 42678)13.2 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"13.213.4
(Xilinx Answer 42730)MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo1.11.3
(Xilinx Answer 42729)MIG 7 Series v1.1-v1.2 QDRII+ - Custom x36 memory part showing the wrong data width1.11.3
(Xilinx Answer 42726)MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component1.11.3
(Xilinx Answer 40578)MIG 7 Series v1.1 - Fixed latency mode is not supported for QDRII+ designs1.11.2
(Xilinx Answer 40579)MIG 7 Series v1.1 - During recustomization of QDRII+ designs, the bank selection page fails to remember previous bank selection1.11.2
(Xilinx Answer 40580)MIG 7 Series v1.1 - SBG324 and FBG484 packages do not have enough banks to fit x36 QDRII+ parts1.11.2
(Xilinx Answer 40871)MIG 7 Series v1.1 - The minimum frequency for QDRII+ designs is 200 MHz1.11.2
General InfoTRCE timing is not guaranteed for all configurations and at high frequencies (above 450 MHz memory clock for QDRII+ SRAM interfaces) 1.11.2
General InfoCreate Custom Part functionality is not supported for EDK designs 1.11.2


MIG 7 Series RLDRAM II

The following table provides known issues for MIG 7 series RLDRAM II.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 55138)MIG 7 Series RLDRAM II - incorrect error message for data mask pin allocation when verifying pin out in MIG GUI1.9Not Resolved
(Xilinx Answer 55136)MIG 7 Series RLDRAM II - timing violation found for "u_phy_write_init_sm/rst_clk_sync_r" path1.9Not Resolved
(Xilinx Answer 54845)MIG 7 Series - v1.8 - No instantiation template provided for VHDL version of the core1.8Not Resolved
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8Not Resolved
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.5Not Resolved
(Xilinx Answer 53919)Design Advisory for MIG 7 Series v1.8 RLDRAM II - Pin Out violation not detected in "Fixed Pin Out" mode or "Verify Pin Changes and Update Design" flow1.81.9
(Xilinx Answer 53439)MIG 7 Series RLDRAM II - Read Leveling Stage 2 calibration can fail with some configurations1.81.9
(Xilinx Answer 53436)MIG 7 Series RLDRAM II - Timing failure from CMD_WR_EN to PRE_FIFO1.81.9
(Xilinx Answer 53375)MIG 7 Series QDRII+ and RLDRAM II/3 - timing paths from PHASER_IN to OSERDES are not analyzed due to missing clock definition1.71.9
(Xilinx Answer 52230)MIG 7 Series RLDRAM II - Traffic Generator in the example design gets stuck after sending write commands1.71.9
(Xilinx Answer 53437)MIG 7 Series RLDRAM II - bit width mismatch for vio_fixed_bl_value causes simulation errors1.71.9
(Xilinx Answer 50752)MIG 7 Series RLDRAM II - combinatorial path can fail timing when using largest components at high speed1.41.7
(Xilinx Answer 50736)MIG 7 Series RLDRAM II - data mismatch errors can occur with traffic generator when set to Burst Length 8 (BL=8)1.51.6
(Xilinx Answer 50699)MIG 7 Series - VCC_AUX can get set incorrectly in certain multi-controller configurations1.51.6
(Xilinx Answer 50696)MIG 7 Series - unable to run the memory clock frequency at 533 MHz using a 200 MHz input clock1.41.6
(Xilinx Answer 47043)MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE software version14.1)1.5NA
(Xilinx Answer 47372)MIG 7 Series - Designs fail during MAP stage when XST "KEEP_HIERARCHY" option is set to "YES" 1.4 Not Resolved
(Xilinx Answer 47385)MIG 7 Series RLDRAMII - Timing violations might occur when Debug Signals feature is enabled 1.5 1.9
(Xilinx Answer 45447)MIG 7 Series RLDRAM II and QDRII+ - skew on the K/K# clocks can cause calibration failures1.31.5
(Xilinx Answer 45764)MIG QDRII+/RLDRAMII - create_ise.bat/.sh fails when Debug Port is Disabled1.41.5
(Xilinx Answer 45721)MIG 7 Series (all design) - System/Reference Clock pins not selectable in two bank Zynq devicesNANA
(Xilinx Answer 42831)MIG 7 Series DDR3/QDRII+/RLDRAM II - Design fails in core generation with single-ended system clock1.21.6
(Xilinx Answer 44341)MIG 7 Series v1.3 RLDRAM II - MAP parameters and UCF constraints are incorrectly generated and cause implementation failures 1.31.4
(Xilinx Answer 44695)MIG 7 Series v1.3 - sys_rst is not validated properly using the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44356)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation 1.31.4
(Xilinx Answer 44352)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Incorrect pinout is generated in the "Verify Pin Changes and Update Design" flow 1.31.4
(Xilinx Answer 44350)MIG 7 Series v1.3 - Does not support -2L speed grade 1.31.4
(Xilinx Answer 44348)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not able to proceed past bank selection or system pins selection page1.31.4
(Xilinx Answer 44018)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Synplify Pro will not be supported in 13.3 1.31.4
(Xilinx Answer 43481)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules 1.31.4
(Xilinx Answer 43100)MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Status signal names have changed to provide uniformity across all interfaces 1.31.3
(Xilinx Answer 42811)MIG 7 Series v1.2 - Setup error on PHY hard blocks due to incorrect timing model1.21.4
(Xilinx Answer 42808)MIG 7 Series v1.2 - Component switching limit error on PHY hard blocks due to incorrect timing model1.21.3
(Xilinx Answer 42836)MIG 7 Series v1.2 - Incorrect PHASER IN and PHASER OUT constraints generated for compatible Artix-7 device1.21.3
(Xilinx Answer 42678)13.2 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"13.213.4
(Xilinx Answer 42725)MIG 7 Series v1.2 - No CC pair available for System Clock1.21.3


MIG 7 Series RLDRAM 3

The following table provides known issues for MIG 7 series RLDRAM 3.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 55419)MIG 7 Series - RLDRAM3 - extra address bits1.8Not Resolved
(Xilinx Answer 54845)MIG 7 Series - v1.8 - No instantiation template provided for VHDL version of the core1.8Not Resolved
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8Not Resolved
(Xilinx Answer 55134)MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure1.5Not Resolved
(Xilinx Answer 53441)MIG 7 Series RLDRAM 3 - data comparison errors are not flagged correctly1.71.8
(Xilinx Answer 52232)MIG 7 Series RLDRAM 3 - tWTR and tRC violations are reported during simulations for 4:1 mode (CMD_PER_CLK=4) and Burst Length 2 (BL=2) configurations1.71.9
(Xilinx Answer 52231)MIG 7 Series RLDRAM 3 - Data Mask pins must be placed in the same byte lane as their corresponding data bytes1.7Not Resolved

MIG 7 Series with Vivado Design Suite
Answer RecordTitleVersion Found Version Resolved
(Xilinx Answer 54584) MIG 7 Series - Needed XDC constraint changes when using a Synplify netlist within Vivado 1.8.a1Not Resolved
(Xilinx Answer 53431)MIG 7 Series DDR2 - Example design's generated through native Vivado IP flow will show X on bi-directional signals when using xsim to simulate 1.8.a11.9.a1
(Xilinx Answer 53376)MIG 7 Series - Potential issues and work arounds with Vivado 2012.4 "Open IP Example Design" feature1.8.a11.9.a1
(Xilinx Answer 52421)MIG 7 Series - Support for Vivado IP Upgrade1.7.a11.8.a1
(Xilinx Answer 52419)MIG 7 Series - "Verify Pin Changes and Update Design" and "Fixed Pin Out" flows do not support uploading XDC files 1.7.a11.8.a1
(Xilinx Answer 52099)MIG 7 Series - Incorrect behavior when using Synplify with a MIG design that uses the I/O Low Power feature 1.61.9.a1
(Xilinx Answer 52284)MIG 7 Series v1.7.a - Inability to delete or rename files can occur on Windows after implementation or simulation scripts have been invoked1.7.a11.9.a1
(Xilinx Answer 52280)MIG 7 Series v1.7.a - Simulations do not work with designs created using the "Open IP Example Design" option in Vivado1.7.a11.9.a1
(Xilinx Answer 52233)MIG 7 Series - Vivado fails in GUI mode when debug signals are enabled1.7.a11.9.a1
(Xilinx Answer 52213)MIG 7 Series - critical warnings are seen in Vivado regarding XDC constraints1.7.a1Not Resolved
(Xilinx Answer 52209)MIG 7 Series - mig.exe crashes when launched from XPS in Vivado1.7.a11.8.a1
(Xilinx Answer 52181)MIG 7 Series - critical warnings are generated when ChipScope cores are used in Vivado1.7.a11.8.a1
(Xilinx Answer 52002) MIG 7 Series - Vivado Simulator scripts have been removed for VHDL designs1.7.a11.8a1
(Xilinx Answer 50705)MIG 7 Series -Vivado Simulator simulations fail in Windows environment across all interfaces1.61.7.a1
(Xilinx Answer 50702)MIG 7 Series - VHD designs fail simulation when using ISIM and Vivado Simulator1.61.7.a1
(Xilinx Answer 47273) MIG 7 Series - How to generate and implement the Example Design in Vivado Design Suite 2012.11.5NA
(Xilinx Answer 47247)MIG 7 Series DDR2/DDR3 - multi-cycle XDC constraints incorrectly set when I/O Power Reduction is disabled 1.5 1.6
(Xilinx Answer 47423)MIG 7 Series RLDRAM II - Missing PHASER_IN constraint causes Placer error1.51.6
(Xilinx Answer 47108)MIG 7 Series DDR2/DDR3 - Synplify Pro fails when "I/O Power Reduction" is enabled1.51.6

Revision History

03/01/2017Deleted reference to AR#55039 in DDR2/3 because the AR itself was deleted for not being a bug
02/08/2017Added 50086, 51296, 51456, and 51687
08/06/2014Added 46782
07/11/2013Added 56682
07/02/2013Added 55013
06/03/2013Updated title
04/15/2013Added 55531
04/03/2013Updated for 14.5 / 2013.1 release
02/12/2013Added 53249
01/17/2013Added 53607
01/10/2013Added 53704
01/08/2013Added 53420
12/18/2012Updated for MIG 1.8 Release
10/24/2012Added 52541
10/16/2012Updated for MIG 1.7 release
07/31/2012Added 42946 and 42944
07/25/2012Updated to include MIG 7 Series Release Notes information
05/10/2012Added 43344
05/08/2012Updated to include all MIG 7 series Release Notes information
03/16/2012Added 46866
03/13/2012Added 46676
03/01/2012Added 46617
02/27/2012Added 46487
01/31/2012Updated to include all MIG 7 Series Release Notes Information. Obsoletes answer records 40050, 41227, and 43099.
01/18/2012Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
46227 MIG 7 Series Solution Center - Top Issues N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47389 MIG 7 Series DDR3 - Multi-controller designs might fail timing in certain configurations N/A N/A
53053 有关 MIG 7 系列 QDRII+ 的设计咨询 - 当出现 CPT_CLK_CQ_ONLY=FALSE 时,会发生读取校准故障 N/A N/A
53136 MIG 7 Series QDRII+ - A latch is incorrectly inferred when using Synplify and CPT_CLK_CQ_ONLY=TRUE N/A N/A
53436 MIG 7 Series RLDRAM II - Timing failure from CMD_WR_EN to PRE_FIFO N/A N/A
53437 MIG 7 Series RLDRAM II - bit width mismatch for vio_fixed_bl_value causes simulation errors N/A N/A
53607 有关 MIG 7 系列 QDRII+ 的设计咨询 - 推断出的锁存器造成写校正故障所需的解决方法 N/A N/A
52124 MIG 7 Series DDR3/DDR2 - Synplify fails due to DQS parameters N/A N/A
53919 有关 MIG 7 系列 v1.8 RLDRAM II 的设计咨询 - 在“固定管脚”模式或“验证引脚更改和更新设计”流程中,检测不到管脚违规问题 N/A N/A
53249 MIG 7 Series - Clock input must be connected manually with NO BUFFER option when multiple cores are generated N/A N/A
54262 MIG 7 Series DDR3 - Dual rank example design incorrectly detects data compare error when reading from second rank address space. N/A N/A
54338 MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection N/A N/A
55531 MIG 7 系列 v1.9 DDR3/DDR2 的设计咨询- 不适用于 PRBS 校正结果 (需要更新 RTL ) N/A N/A
55602 MIG 7 Series QDRII+ - Data failures can occur when Fixed Latency mode is enabled N/A N/A
55884 MIG 7 Series QDRII+ - "pi_edge_adv" can be stuck during calibration, which may lead to data failures N/A N/A
46782 MIG 7 Series DDR2 SDRAM - "Error:MapLib:1121" occurs when KEEP HIERARCHY is set to "YES" N/A N/A
67023 MIG 7 Series RLDRAM3 - Write Calibration failures can occur when Read Latency (RL) is larger than 12 N/A N/A
50086 MIG 7 Series v1.5 DDR3 - Updated Trace Matching Requirement for CK/CK# and DQS/DQS# N/A N/A
51296 设计咨询 - ISE 14.2 和 Vivado 2012.2 Design Suite 版本中 7 系列包延迟时间 (Package Flight Time) 的改变 N/A N/A
51456 有关 Artix-7 FPGA 设计咨询的主要答复记录 N/A N/A
51687 设计咨询 MIG 7 系列 DDR3/DDR2 – v1.7 中使用 XADC 模块进行温度监控器校准的功能被添加到所有的 DDR3/DDR2 设计 (ISE 14.3/Vivado 2012.3) N/A N/A

相关答复记录

AR# 45195
日期 04/19/2017
状态 Active
Type 版本说明
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
的页面