AR# 45330


14.x Timing Analyzer - Non-zero Phase Error is seen in paths with same clock


Phase Error (120 ps) is included when analyzing paths clocked by the same clock.

Paths for end point:

phy_top_inst/ollm_rx_top_inst/ollm_rx_err_detect_inst/pk_crc_in_error_cond_standard_case (SLICE_X138Y86.B6), 364 paths


Slack (setup path): 0.054 ns (requirement - (data path - clock path skew + uncertainty))
Source: srio_module_inst/ul_srio_dsp1/srio_dut_inst/srio_wrapper_inst/phy_wrapper_inst/srio_phy_inst/U0/phy_top_inst/
ollm_rx_top_inst/ollm_rx_datapath_inst/masked_rx_data_stg1_49 (FF)
Destination: srio_module_inst/ul_srio_dsp1/srio_dut_inst/srio_wrapper_inst/phy_wrapper_inst/srio_phy_inst/U0/phy_top_inst/
ollm_rx_top_inst/ollm_rx_err_detect_inst/pk_crc_in_error_cond_standard_case (FF)
Requirement: 4.000 ns
Data Path Delay: 3.682 ns (Levels of Logic = 5)
Clock Path Skew: -0.068 ns (0.870 - 0.938)
Source Clock: phy_clk_dsp1 rising at 0.000 ns
Destination Clock: phy_clk_dsp1 rising at 4.000 ns
Clock Uncertainty: 0.196 ns
Clock Uncertainty: 0.196 ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070 ns
Discrete Jitter (DJ): 0.135 ns
Phase Error (PE): 0.120 ns

It should be zero, should it not?


In this design, the signal "phy_clk_dsp1" is driven by a BUFGMUX, whose inputs are fed by two different outputs of an MMCM (CLKOUT0 and CLKOUT1). The timing engine is assuming a worst-case analysis, which means PLL_ADV_CLKOUT_TO_CLKOUT_PHASE_ERROR (120 ps defined in Speedfiles) is included.

AR# 45330
日期 03/07/2013
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Type 综合文章
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