Bitstream Compatibility Between Initial ESversus General ES Silicon:
The Initial ES bitstream cannot be used with General ES silicon and vice versa.Version 1.5 of the 7 Series FPGA Transceivers Wizard in ISE Design Suite 13.4 generates the GTX settings that only support the Initial ES Silicon settings, and version 1.6 of the Wizard supports only the General ES Silicon settings.
Initial ES Errata Items:
TXOUTCLK and RXOUTCLK ports
For General ES Silicon, the restrictions on using TXOUTCLK and RXOUTCLK ports are removed.
QPLL use mode
For General ES Silicon, the QPLL use mode and the coarse calibration module work to ensure optimal margin acrossvoltage. Temperature variationsare not required.
Receiver Link Margin
For General ES Silicon, the receiver link margin is not affected when in full rate mode (RXOUT_DIV = 1).
For General ES Silicon, the CPLL, when operated at 3.1 GHz or above, does not exhibit higher jitter when MGTAVTT is higher than nominal.
Transmitter Electrical Idle
For General ES Silicon, the transmitter common mode voltage is as expected when TX electrical idle is enabled.
IEEE Standard 1149.6 for GTX Transceivers
For General ES Silicon, the IEEE Standard 1149.6 (ACJTAG) boundary-scan test commands EXTEST_PULSE and EXTEST_TRAIN are not supported.
Software use model changes in ISE 13.4:
The GTX software use model changes and requirements in Initial ES Silicon, as captured in (Xilinx Answer 43339), are referenced here and discuss what that translates to when using ISE Design Suite 13.4.
GTXE2_COMMON Use Model Change
The GTXE2_COMMON instantiation when not using QPLL is still required for General ES silicon. This is necessary for the correct BIAS_CFG to propagate through; otherwise, BIAS_CFG, an attribute of the GTXE2_COMMON module, will be set incorrectly. The GTXE2_COMMON is automatically instantiated when using ISE 14.2 software version, otherwiseit must be instantiated manually as described in (Xilinx Answer 43339).
IBUFDS_GTE2 Use Model Change
The IBUFDS_GTE2 software issue causing incorrect reference clock swing for the Quad has been fixed in the ISE 13.4 software model. Therefore,the work-around with both IBUFDS_GTE2 instantiations per Quad is no longer required. The CLKSWING_CFG has been updated from 1-bit boolean to2-bit binary value with the default set correctly to 2'b11.
If the IBUFDS_GTE2 instantiation, prior to ISE Design Suite 13.4, did not have the parameter CLKSWING_CFG specifically typed out, then the HDL is directly forward-compatible in ISE software version 13.4 and beyond. Keeping the extra IBUFDS_GTE2 instance will not cause any issues.
If the IBUFDS_GTE2 instantiation, prior to ISE Design Suite 13.4, did have the parameter CLKSWING_CFG specifically typed out, that value needs to be updated to a binary value of 2'b11. Optionally, the extra IBUFDS_GTE2 instance could be removed.