UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45424

Virtex-6 FPGA GTH Transceiver Wizard v1.9 - VHDL code of example design is not implementing correctly

描述

This answer record discusses an issue with generating an example design in VHDL with the Virtex-6 FPGA GTH Transceiver Wizard v1.9.

解决方案

When generating the VHDL example design for Virtex-6 FPGA GTH Transceivers with the wizard version 1.9, the design will not implement, but generates the following error message:

ERROR:HDLCompiler:69 - "C:\...\GTH_Transmitter\gth_transmitter_quad.vhd" Line 890: is not declared.

Generating the design with Verilog runs through the implementation process. This is fixed in thewizard version 1.10 in ISE 13.4 software.
AR# 45424
日期 12/15/2012
状态 Active
Type 综合文章
器件
  • Virtex-6 HXT
Tools
  • ISE Design Suite - 13.3
IP
  • Virtex-6 FPGA GTH Transceiver Wizard
的页面