AR# 45485


CORE Generator - "ERROR:sim - Unknown language preference 'None'"


IP Core generation fails with the following message:

"ERROR:sim - Unknown language preference 'None'."


This error can occur when neither VHDL nor Verilog outputs are chosen in the project options. This state should only be possible if a user has edited the ".xco" file outside of the CORE Generator tool.

The use case of selecting neither VHDL nor Verilog is very rare; it is only available by editing the ".xco" files.

Before generating the core, verify that either the vhdlsim or verilogsim property is set to "true".
AR# 45485
日期 05/26/2014
状态 Archive
Type 已知问题
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