When a .txt file is included as a source file in the IP Packager, it is marked as a "text" file in the component.xml file created by the packager.
However, the generated <core_name>.prj file has the .txt file listed as "vhdl."
During Synthesis, XST tries to parse the Verilog function as VHDL and will likely fail with a syntax error.
The Verilog ISE Example "Wave Generator" project has a "clogb2.txt" file that is called by five of the other <source>.v files.
This .txt file contains a single short Verilog function. The function is called by the other Verilog files with: 'include "clogb2.txt"
However, if this project is packaged and used as an IP, synthesis will error out on the "//" verilog comment delimiters even if the entire project is set as Verilog.
The IP Packager is packaging the text file correctly but CORE Generator and the Vivado/PlanAhead IP generation tool are incorrectly attempting to synthesize files that are not marked as vhdl or verilog.
This issue has been fixed in Vivado 2012.3 and ISE 14.3 Design Suites.
Files that are not added with a specific language will not be automatically assigned or compiled with a defined HDL type.