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AR# 45516

System Generator for DSP - System Generator GUI reports incorrect latency value of Divider Generator (AXI) v4.0. Is there a workaround?

描述

The Divider Generator block in the System Generator model reports a latency of 21 for the particular core settings. However, all simulations (both in Simulink and ISim) and the CORE Generator indicate that the core should have 30 cycles of latency for the same settings.Is there a workaround?

解决方案

There is an issue with the DivGen 4.0 block Latency field. The workaround is to run simulation to determine the correct latency value.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
29595 Xilinx DSP Tools, System Generator for DSP, and AccelDSP Synthesis Tool - Release Notes and Known Issues N/A N/A
AR# 45516
日期 05/20/2012
状态 Active
Type 已知问题
Tools
  • System Generator for DSP - 13.3
  • System Generator for DSP - 13.4
的页面