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AR# 45602

Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-around for Initial Engineering Sample (ES) Silicon for Aurora Cores

描述

This answer record contains information on issues, work-arounds, and attribute updates for Aurora cores (Aurora 8B10B v7.1 / Aurora 64B66B V6.1) that use Kintex-7 and Virtex-7 FPGA GTX Transceiver Initial Engineering Sample (ES) Silicon (CES9937).

解决方案

GTX Transceiver attribute updates are required for ES Silicon to work in hardware.

Please refer to the master (Xilinx Answer 43244) for the latest updates.

Below are the hardware configurations validated in Kintex-7 FPGA KC724 board-to-board setup:

Aurora 8B10B v7.1 core:

Validated core configuration:

Aurora lanes : 4
Line rate : 4.0 Gbps
GT reference clock : 100.0 MHz
Lane Width : 2
Dataflow : Duplex

The GTX Transceiver settings file (aurora_8b10b_v7_1_gt.v) is attached for reference.

Aurora 64B66B v6.1 core:

Validated core configuration:

Aurora lanes : 1
Line rate : 3.125 Gbps
GT reference clock : 156.25 MHz
Lane Width : 8
Dataflow : Duplex

The GTX Transceiver settings file (aurora_64b66b_v6_1_gt.v) is attached for reference.


Note:

  • TX/RX Buffers are enabled in both Aurora Cores
  • Validated design uses CPLL. Please refer to the master AR for QPLL settings (applicable only for Aurora 64B66B core)
  • QPLL not supported in the Aurora 8B10B core
  • Validation has been done in Kintex-7 KC724 board-to-board setup but the settings provided can be used with Virtex-7 devices also.

附件

文件名 文件大小 File Type
aurora_8b10b_v7_1_gt.v 38 KB V
aurora_64b66b_v6_1_gt.v 37 KB V

链接问答记录

主要问答记录

AR# 45602
日期 01/28/2015
状态 Active
Type 综合文章
器件
  • Kintex-7
  • Virtex-7
IP
  • Aurora 8B/10B
  • Aurora 64B/66B
Boards & Kits
  • Kintex-7 FPGA KC724 Characterization Kit
的页面