AR# 45647


MIG 7 Series v1.4 DDR2/DDR3 - OCLK_DELAY Calibration


Starting with MIG 7 Series v1.4, an additional OCLK_DELAY calibration stage has been added for DDR2/DDR3 designs. 

This new stage of calibration is performed before the Read Leveling stage of calibration, and is required to center align write DQS in the write DQ window per byte to help improve write timings.

Note: Xilinx recommends upgrading existing 7 Series DDR3 designs to MIG 7 Series v1.4 to include this calibration stage.


The OCLK_DELAY calibration requires reads to be correct.

Because the OCLK_DELAY calibration occurs before the Read Leveling stage of calibration, a Multi Purpose Register (MPR) read leveling calibration is performed for correct read functionality before the OCLK_DELAY calibration begins. 

During OCLK_DELAY calibration, the algorithm performs the following:

  1. Decrements the OCLK_DELAY taps from 30 until either a DQ edge is detected or a tap value of 0. 
  2. Increments the OCLK_DELAY taps back to 30 and begins DQ edge detection with every increment past 30 taps. 
  3. Places DQS in the center of the two detected edges.
  4. Uses a pattern calibration for all subsequent stages so that it can differentiate between early, on time, and late reads and writes.

Without the OCLK_DELAY calibration stage added it is possible the Phase between DQS and DQ during writes could be out of specification and cause calibration failures. 

In addition to the new OCLK_DELAY calibration stage, since the MIG 7 Series v1.4 release an additional update to the OCLK_DELAY is required for all users working in hardware. 

For this reason, Xilinx recommends upgrading to MIG 7 Series v1.4 and installing the patch provided in (Xilinx Answer 45653).

The OCLK_DELAY calibration is also planned to be added for QDRII+ and RLDRAMII designs starting in software version 14.1. 

For more details, refer to (Xilinx Answer 45447).

AR# 45647
日期 08/21/2014
状态 Active
Type 综合文章
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