This answer record highlights the important requirements and known issues for the Kintex-7 FPGA General Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Kintex-7 325T and 410T General ES devices(marked as CES). Additional silicon limitations might exist, so please reference the 7 Series FPGA errata online. The errata document also outlines specific part markings and JTAG Revision IDs.
This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
Software Known Issues
All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on General ES FPGA devices is dependent on Xilinx hardware validation, which will be ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records (below) for the most recent information. The list below includes all Pre-Production IP cores that have been hardware validated on General ES at this time:
This list will be updated as hardware validation is completed. If there are further questions about hardware validation for a particular IP core, please contact a Field Application Engineer.
IP Known Issues
Other Important Items:
09/24/2012 - Minor update; no change to content
02/23/2012 - Updated IP Requirements and IP Known Issues sections
01/18/2012 - Added Answer Record 45870
01/11/2012 - Initial Release