For the most recent updates to the IP installation instructions for this core, please go to:
For system requirements:
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.4 solution. For the latest core updates, see the product page at:
- ISE 13.4 software support
- Packet FIFO feature addition
-Support added for Virtex-7,Virtex-7 -2L,Virtex-7 -2G,Virtex-7 XT,Kintex-7,Kintex-7 -2L, Artix-7, Zynq-7000*
-(Xilinx Answer 45744) ISE 13.4 Coregen FIFO Generator v8.4- Not able to open core documentation in coregen.
- In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
- CR 467240
- AR 31379
- When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write.
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
For more information and additional workaround see Answer Record 41099.
- The FIFO Generator GUI is allowing the user to select the FULL Threshold Assert Value lesser than EMPTY Threshold Assert Value for AXI FIFO.
- CR 613264
Workaround: To work around this issue, select FULL Threshold Assert Value greater than EMPTY Threshold Assert Value
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Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.