描述

This answer record contains the Release Notes for the LogiCORE IP QSGMII, first released in the ISE 13.4 design tools, and includes the following:

• New Features
• Supported Devices
• Resolved Issues
• Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.

For LogiCORE IP QSGMII v2.0 and later Release Notes, see (Xilinx Answer 54668).

解决方案

Key Features

• Designed to Cisco's proprietary QSGMII specification, version 1.2
• Implements 4 lanes of 10/100/1000 Mb/s channels
• IEEE 802.3-2008 Clause 36 implementation of PCS (Physical Coding Sublayer) for encapsulation, line encoding, and link synchronization
• Available at no charge in the CORE Generator tool
• Supports internal or external GMII for interfacing to a MAC or customer logic
• Integrated with the Xilinx 7 Series embedded transceivers
• Available in VHDL or Verilog netlist simulation model

New Features for latest v1.4 core

• ISE 14.3 tool support
• Vivado 2012.3 tool support
• Zynq-7000 SoC support
  

Supported Devices for latest v1.4 core

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
  

NOTE: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues

This table correlates the core version to the first ISE or Vivado design tools release version in which it was included.

The following table provides known issues for the 7 Series Integrated Block for PCI Express.

NOTE: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

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