This answer record contains the Release Notes for the LogiCORE IP QSGMII, first released in the ISE 13.4 design tools, and includes the following:
For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.
For LogiCORE IP QSGMII v2.0 and later Release Notes, see (Xilinx Answer 54668).
New Features for latest v1.4 core
Supported Devices for latest v1.4 core
NOTE: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
This table correlates the core version to the first ISE or Vivado design tools release version in which it was included.
|Core Version||ISE Version||Vivado Version|
The following table provides known issues for the 7 Series Integrated Block for PCI Express.
NOTE: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Version Resolved|
|(Xilinx Answer 58108)||Update to RX termination for 7 Series GTH||v1.4||Work-around in answer record|
|NA||Updates to 7 Series GTP/GTX/GTH Transceiver wrapper files for production support||v1.4||v1.5|
|(Xilinx Answer 47513)||Vivado 2012.1 - ERROR PhysDesignRules:1259||v1.3|
|(Xilinx Answer 47510)||Vivado 2012.1 - CRITICAL WARNING messages seen in example design||v1.2rev1|
|(Xilinx Answer 47666)||Vivado 2012.1 - Guidance for Simulating Ethernet IP cores||v1.2||NA|