Youneed to either target a smaller design such that an empty bank is available for System Control and Reference Clock pins, or use a voltage standard for System Control and Reference Clock that are compatible with the I/O standard used for the memory interface.
For information on 7 Series I/O standard compatibility, see the7 Series SelectIO Resource User Guide (UG471):
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
NOTE: LVDS inputs do not require a specific Vcco levelprovided that recommended operating conditions are metand DIFF_TERM =FALSE.Internal termination, (i.e., DIFF_TERM=TRUE), is only supported on 1.8v HP banks or 2.5v HR banks)
AR# 45721 | |
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日期 | 10/11/2012 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |