AR# 45765

MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim

描述

MIG v3.91 Virtex-6 DDR3/DDR2 72-bit and 144-bit AXI Lite designs may fail in simulation with a segmentation fault when using ModelSim.

解决方案

This onlyaffects Virtex-6 DDR3/DDR2 AXI Lite 72-bit and 144-bit designs, but can be worked around by replacing the "-novopt" command with "-voptargs="+acc"" in the sim.do file located in the ./sim directory, or the user can use ISE Simulator.

This issue will be fixed in a future version of ModelSim.

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链接问答记录

主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
45194	MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4	N/A	N/A

相关答复记录

Answer Number	问答标题	问题版本	已解决问题的版本
45194	MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4	N/A	N/A

AR# 45765
日期	07/02/2012
状态	Active
Type	已知问题
器件	Kintex-7 Artix-7 Virtex-7
IP	MIG 7 Series

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