This simple reference design integrates a Verilog module generated from the AutoESL tool into a System Generator model. The design incorporates a SysGen FFT block whose output is fed to a black box "power_stats" module. The "power_stats" module was generated from C source using the AutoESL tool. The AutoESL tool design calculates the power of each FFT output bin and keeps track of the minimum, maximum, and whether the power crosses a user-defined threshold value. A global "ce" (clock enable) signal was generated as an option out of the AutoESL tool to meet the interface rules for black boxes in System Generator.
Design Languages (HDL/SW): System Generator and the AutoESL tool
Design Reference Document
Two ZIP files are included, the AutoESL tool project and the System Generator project. The System Generator project includes the model and a config.m file (power_stats_config.m) that links the block box component in System Generator to the Verilog source. The config.m file needs to be edited to specify the new path to the Verilog source (which is contained in the AutoESL tool ZIP file) once unzipped.
| 文件名 | 文件大小 | File Type |
|---|---|---|
| SysGen_AutoESL_model.zip | 18 KB | ZIP |
| FFT_stats_AutoESLproj.zip | 1 MB | ZIP |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 47431 | Xilinx Vivado HLS Solution Center - Design Assistant | N/A | N/A |