You can communicate to Little Endian flash devices by swapping the appropriate data and address lines at the top level of your XPS design. No HDL modification should be necessary. The EMC data sheets (both AXI and PLB) give an example of how to connect the EMC to Intel StrataFlash; you can find this document under $XILINX_EDK/hw/XilinxProcessorIPLib/pcores/[AXI or XPS EMC]/doc
Note that while the AXI interconnect will communicate to the EMC via Little Endian, the AXI EMC core will still communicate to the flash device in Big Endian format.