AR# 45870


ISE 13.4 BitGen - Unexpectedly long delay through input when using low voltage standard on 7 series FPGAs


In Kintex-7 FPGA using 13.4 and lower software versions, there is an input timing issue when only assigning 1.2, 1.5, or 1.8V inputs into a bank. When only inputs are placed in the bank, a bit is not set properly to configure the input receivers. Therefore, a delay of ~20ns through the input buffer exists at 1.2V. At voltages of 1.5 and 1.8 the delay is much shorter, but still does not meet the data sheet numbers.


To work around this issue, instantiate an output buffer of the same voltage as the inputs in the bank.

If placing an output buffer in the same bank is not an option, please contact Xilinx Technical Support for assistance.
AR# 45870
日期 02/29/2012
状态 Active
Type 综合文章
器件 More Less
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