General Description: When trying to synthesize VHDL code with don't cares, Express ignores anything that contains don't cares and synthesizes that section of code to a constant.
For example, a code segement like this
if (a= "1--1" and b = "--00") then c <= '1'; else c <= '0'; end if;
would result in warnings like this:
Comparisons to a 'don't care' are treated as always being false. This may cause simulation to vary from synthesis.
One solution is to compare the individual bits rather than the entire bus with the don't cares in them. Instead of the code above, you would write:
if ((a(3)= '1' and a(0)='1') and (b(1)= '0' and b(0)='0')) then c <= '1'; else c <= '0'; end if;
Another solution is to build your own std_match function to compare the vector to a mask string. This procedure becomes easier to implement (compared to the first solution) as the comparisons become more complex.
--first, declare the match type that allows don't cares type match_t is ('0', '1', '-'); type match_a_t is array (natural range <>) of match_t;
--next, create the function that will perform the compare function std_match (l : std_logic_vector; r : match_a_t) return boolean is variable flag : boolean; begin flag := true; for i in l'range loop flag := flag and ((r(i)='-') or (r(i)='1' and l(i)='1') or (r(i)='0' and l(i)='0')); end loop; return flag; end std_match;
--declare the mask that will be used in the comparison constant maskA : match_a_t (A'range) := "-11-"; constant maskB : match_a_t (B'range) := "--00";
signal comp1, comp2 : boolean;
-- compare the signal against the mask comp1 <= std_match(A, maskA); comp2 <= std_match(B, maskB);
--this process creates the same logic as resolution 1 process(comp1, comp2) begin if (comp1 and comp2) then C <= '1'; else C <= '0'; end if; end process;