UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45985

7 Series - How do you limit reverse biasing of VCCO when input is being driven by a 3.3V signal before Vcco is powered?

描述

The 7 Series FPGAs data sheet states that the voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle, in order to maintain device reliability levels for VCCO voltages of 3.3V in HR I/O banks and configuration bank 0. 

If the VCCO rail is not powered and I/O pins are driven to 3.3V by another device, the I/O ESD diode will be forward biased and power the VCCO rail. If VCCAUX has not been powered to 1.8V, this will result in the 2.625V specification being exceeded.

How can I ensure that I do not exceed 2.625V on VCCO?

解决方案

If you design is connecting an external resistor between VCCO and GND, this will provide a path that shunts the current and limits the reverse biasing voltage to below the 2.625V.

As per the data sheet, the maximum current into an I/O when forward biasing the diode must be less then 10 mA, so please make sure that the design adheres to this requirement.


 

Placing a resistor value of 262 ohm per pin (10 mA * 262 Ohms < 2.625V), that is, forward biasing the diode before VCCAUX is present will prevent the VCCO supply from going above 2.625V.

When the device is in normal operation, the resistor will burn 41.6 mW of power ( P=V^2 * R= 3.3^2 / 262). If several pins on the same supply are forward biasing the diode before VCCAUX is present, then the parallel equivalent resistor can be placed between the VCCO supply and GND. For example, if 10 I/Os are driving before VCCAUX is present, then the resistor would have to be 26 Ohms.

Note: Xilinx does not recommend driving I/Os when VCCO in unpowered. For further information, see (Xilinx Answer 37347)

Note: This suggestion is only suitable for a small number of pins being driven to 3.3V before VCCO is powered.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
50802 7系列--上电后,I/O管脚处于何种状态? N/A N/A
AR# 45985
日期 10/04/2016
状态 Active
Type 综合文章
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Virtex-7 HT
  • Spartan-7
  • Less
的页面