Description: The path through the asynchronous preset or clear of
an FDCP in the XC9500 family cannot be analysed using the timing
analyser. The path up to the preset or clear *is* measurable, but not
the path through the flop from the pre/clr to the output.
The path delay may be calculated manually using the XC9500 timing
tin + tptsr + t aoi + tout
This would be from a pad, through a buffer to the preset/clear, through
the flop, through the output buffer and to the opad.