You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
Spartan-6 9K block RAM work-around - The solution in Answer Record 39999 does not work when using an XPS core as a submodule
The Spartan-6 9K block RAM work-around in (Xilinx Answer 39999) does not work when using an XPS core as a submodule.
(Xilinx Answer 39999) explains how the XST switch "-infer_ramb8 NO" should be set to block the inference of 9K block RAM in XST.
The work-around of applying the three switches to XST, MAP and BITGENdescribed in (Xilinx Answer 39999) works correctly when using the ISE flow only.
However, for designs which contain XPS cores in the ISE project, the required XST switch is not passed to the EDK XST options.
To work around this issue, follow these steps:
- Ensure all the required switches are set as described in (Xilinx Answer 39999).
- Open XPS project and generate netlist.
- Open the synthesis directory that was created in the EDK project directory.
- Edit the top-level .scr file to include the XST switch: "-infer_ramb8 No".
- Run XST from the command line using the following command:xst -ifn "<project name>_xst.scr".
- Add the newly created .ngc file as a source in the ISE project.
- Add the UCF from the EDK project and make sure that the correct hierarchy is applied to the nets.
- Run through the ISE flow again.
- Spartan-6 LX
- Spartan-6 LXT