UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46338

Spartan-6 9K block RAM work-around - The solution in Answer Record 39999 does not work when using an XPS core as a submodule

Description

The Spartan-6 9K block RAM work-around in (Xilinx Answer 39999) does not work when using an XPS core as a submodule.

(Xilinx Answer 39999) explains how the XST switch "-infer_ramb8 NO" should be set to block the inference of 9K block RAM in XST.

The work-around of applying the three switches to XST, MAP and BITGENdescribed in (Xilinx Answer 39999) works correctly when using the ISE flow only.

However, for designs which contain XPS cores in the ISE project, the required XST switch is not passed to the EDK XST options.

解决方案

To work around this issue, follow these steps:

  1. Ensure all the required switches are set as described in (Xilinx Answer 39999).
  2. Open XPS project and generate netlist.
  3. Open the synthesis directory that was created in the EDK project directory.
  4. Edit the top-level .scr file to include the XST switch: "-infer_ramb8 No".
  5. Run XST from the command line using the following command:xst -ifn "<project name>_xst.scr".
  6. Add the newly created .ngc file as a source in the ISE project.
  7. Add the UCF from the EDK project and make sure that the correct hierarchy is applied to the nets.
  8. Run through the ISE flow again.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
39999 Spartan-6 FPGA 设计咨询 - 9K Block RAM 初始化支持 N/A N/A
AR# 46338
创建日期 05/02/2012
Last Updated 12/15/2012
状态 Active
Type 综合文章
器件
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • EDK - 13.4
  • EDK - 14.1