AR# 4635


SYNPLIFY: Why is an IBUF inferred between the BUFGDLL/IBUFG and clock-pad?


Keywords: Virtex, Synplify, bufgdll, ibufg

Urgency: Hot

General Description:
Why is Synplify inferring an IBUF between
BUFGDLL/IBUFG and the clock-pad?


This is fixed in Synplify 5.1.2 and later. However, users may
alternatively use (Xilinx Solution 4508) to place a black_box_is_pad
attribute on the I pin of the BUFGDLL, or IBUFG.

This will keep Synplify from infering an IBUF on the clk signal.
The BUFGDLL assumes that the source clock is an external signal
and therefore the signal that drives the BUFGDLL I pin may only
be sourced by an external input port.

Otherwise, NGDBUILD will error:

ERROR:basnu:114 - logical net "clk_c" has multiple drivers
WARNING:basnu:123 - input pad net "clk_c" has an illegal input buffer
ERROR:basnu:142 - input pad net "clk_c" has an illegal connection
AR# 4635
日期 10/05/2008
状态 Archive
Type 综合文章
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