设计助手
Xilinx 7 Series FPGA Solution Center - Design Assistant
The 7 Series FPGA Design Assistant walks you through the recommended design flow for 7 series FPGAs while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with 7 series FPGAs.
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
First, select the design phase for which you have a question or are troubleshooting an issue related to your 7 series FPGA design. This ensures that the Design Assistant points you to the information you need to move forward with your design.
(Xilinx Answer 46433) - Getting Started with 7 series FPGAs
(Xilinx Answer 46489) - Designing for 7 series FPGAs
(Xilinx Answer 46520) - Board Level Considerations
(Xilinx Answer 46719) - Troubleshooting - Clocking, Fabric, block RAM/FIFO
* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.
技术文档
7 Series FPGA Documentation - What documentation should I review to find out if the 7 series FPGA features and specifications are right for my system?
What documentation should I review to find out if the 7 series FPGA features and specifications are right for my system?
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
The 7 Series FPGA Documentation Center contains all 7 series FPGA related documentation:
http://www.xilinx.com/support/documentation/7_series.htm
The following documents are available:
- 7 Series FPGAFamily Overview
- Artix-7 FPGA Data Sheet: DC and Switching Characteristics
- Kintex-7 FPGA Data Sheet: DC and Switching Characteristics
- Virtex-7 FPGA Data Sheet: DC and Switching Characteristics
- 7 SeriesErrata
- 7 SeriesUser Guides
Use the7 Series Family Overview to understand the features available in the7 series FPGA device family and view the differences among the devices within the 7 series FPGA family to assist in product selection.
Use the7 Series FPGA Data Sheets to review the DC and Switching Characteristic specifications for the7 series device family.
Review the7 Series Errata to determine whether the device you are considering has any exceptions to data sheet specifications.
Review the7 Series User Guides to understand usage details for the7 series FPGA resources.
设计咨询
Design Advisory Master Answer Record for Kintex-7 FPGA
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
This Design Advisory covers the Kintex-7 devices and related issues that impact Kintex-7 FPGA designs.
Design Advisories Alerted on April 17th, 2017
04/17/2017 | (Xilinx Answer 69034) | Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential IO Standards. |
Design Advisories Alerted on March 28, 2016
03/28/2016 | (Xilinx Answer 66173) | Design Advisory for Vivado 2015.4 - Vivado Timing WNS Alert - Missing Timing Arc on BUFR to BUFG clock path causes hold violations on board |
Design Advisories Alerted on November 10, 2014
11/10/2014 | (Xilinx Answer 62631) | Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs | [SECURITY] |
Design Advisories Alerted on September 22, 2014
09/22/2014 | (Xilinx Answer 61875) | Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete. |
Design Advisories Alerted on June 16, 2014
06/16/2014 | (Xilinx Answer 60845) | Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation |
06/16/2014 | (Xilinx Answer 59294) | Design Advisory GT wizard - CPLL causes power spike on power up for 7 series Transceivers |
Design Advisories Alerted on May 26, 2014
05/26/2014 | (Xilinx Answer 60356) | Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates |
05/26/2014 | (Xilinx Answer 45360) | Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps |
Design Advisory Alerted on January 20, 2014
01/20/2014 | (Xilinx Answer 59035) | Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2 |
Design Advisories Alerted on November 25, 2013
11/25/2013 | (Xilinx Answer 58244) | Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode |
11/25/2013 | (Xilinx Answer 45360) | Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver; added reference to the user guide UG476 for RX_DFE_KL_CFG2 setting |
Design Advisory Alerted on October 23, 2013
10/23/2013 | (Xilinx Answer 51554) | Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs |
Design Advisory Alerted on September 16, 2013
09/16/2013 | (Xilinx Answer 57193) | Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed |
Design Advisory Alerted on August 26, 2013
08/19/2013 | (Xilinx Answer 57045) | Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration |
Design Advisory Alerted on August 5, 2013
08/05/2013 | (Xilinx Answer 55009) | Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs |
Design Advisory Alerted on May 20, 2013
05/16/2013 | (Xilinx Answer 55009) | Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs |
Design Advisories Alerted on May 13, 2013
05/13/2013 | (Xilinx Answer 55366) | Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - Transceiver Wizard Sets Suboptimal RX Termination Use Modes |
05/13/2013 | (Xilinx Answer 55791) | Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 |
Design Advisories Alerted on April 3, 2013
04/03/2013 | (Xilinx Answer 55009) | Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode |
04/03/2013 | (Xilinx Answer 50906) | Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices |
Design Advisory Alerted on January 21, 2013
1/17/2013 | (Xilinx Answer 53740) | Updated Design Advisory for 7-Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature. |
Design Advisory Alerted on December 18, 2012
12/13/2012 | (Xilinx Answer 45360) | Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB. |
Design Advisories Alerted on November 5, 2012
10/31/2012 | (Xilinx Answer 50617) | Updated Design Advisory for Kintex-7 and Virtex-7 FPGA Production GTX Transceivers with references to specific devices; updated the bitstream compatibility section |
10/25/2012 | (Xilinx Answer 50906) | Updated Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices; updated for 14.3/2012.3 release |
Design Advisories Alerted on October 29, 2012
10/25/2012 | (Xilinx Answer 52193) | Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode |
Design Advisories Alerted on October 22, 2012
10/22/2012 | (Xilinx Answer 45360) | Updated the RXCDR_CFG values in the Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver |
10/22/2012 | (Xilinx Answer 50617) | Updated the bitstream compatibility section in the Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceiver |
Design Advisory Alerted on October 15, 2012
10/15/2012 | (Xilinx Answer 51884) | Design Advisory for Kintex-7 and Virtex-7 GTX Production Silicon CDR Attribute Updates |
Design Advisory Alerted on September 10, 2012
09/10/2012 | (Xilinx Answer 51580) | Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for block Ram (BRAM) or FIFO Components for PERIOD constraint analysis |
Answer Records Upgraded to Design Advisories
09/10/2012 | (Xilinx Answer 45781) | Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option |
Design Advisory Alerted on August 20, 2012
08/17/2012 | (Xilinx Answer 50906) | Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices |
08/20/2012 | (Xilinx Answer 51296) | Design Advisory - 7 Series Package Flight Time changes in ISE 14.2 and Vivado 2012.2 release |
Design Advisories Alerted on July 25, 2012
07/19/2012 | (Xilinx Answer 47817) | Updated Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up/Power-down with additional current draw when following the recommended sequence, with information about duration of current draw, simultaneous power-up and more FAQs. |
07/19/2012 | (Xilinx Answer 45360) | Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX General ES Transceiver with RX_DFE_XYD_CFG value. |
07/19/2012 | (Xilinx Answer 50617) | Design Advisory for the Kintex-7and Virtex-7 FPGA Production GTX Transceivers. |
Design Advisories Alerted on July 2, 2012
06/28/2012 | (Xilinx Answer 45360) | Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated GTX software use mode changeswith the latest GTXE2_COMMON use model change information. |
Design Advisory Alerted on May 8, 2012
05/07/2012 | (Xilinx Answer 47248) | Design Advisory for the Kintex-7 FPGA - XC7K325T CES9937 Initial Engineering Sample (IES) Supported in ISE 13.4 only |
Design Advisory Alerted on March 26, 2012
03/22/2012 | (Xilinx Answer 45360) | Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated RXCDR_CFG setting for half-rate mode. |
Design Advisory Alerted on February 27, 2012
02/23/2012 | (Xilinx Answer 45360) | Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon to include new RXCDR_CFG settings and a link to GTX software known issues/use mode changes. |
Design Advisory Alerted on January 30, 2012
01/24/2012 | (Xilinx Answer 45360) | Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon |
Design Advisory Alerted on January 16, 2012
01/10/2012 | (Xilinx Answer 45633) | Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified |
Design Advisory Alerted on November 21, 2011
11/21/2011 | (Xilinx Answer 44174) | Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup |
Design Advisory Alerted on July 6, 2011
07/06/2011 | (Xilinx Answer 42615) | Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 design tools |
面向 Virtex-7 FPGA 设计咨询的主要答复记录
针对一般设计过程出现的重大问题创建设计咨询答复记录,精选后用于赛灵思提醒通知系统。
此设计咨询包含 Virtex-7 FPGA 及影响 Virtex-7 FPGA 设计的相关问题。
2017 年 4 月 17 日发布的设计咨询提醒
04/14/2017 | (赛灵思答复记录 69034) | 面向 7 系列、UltraScale 和 UltraScale+ 的设计咨询,Vivado 2016.3 之前的所有版本均未包含差分 I/O 标准的飞行时间延迟。 |
2016 年 3 月 28 日发布的设计咨询提醒
03/24/2016 | (赛灵思答复记录 66173) | 面向 Vivado 2015.4 的设计咨询 - Vivado 最差负时序裕量 (Timing WNS) 提醒 - BUFR 到 BUFG 的时钟路径上缺失时序弧 (arc),导致开发板上出现保持时间违例 |
2015 年 1 月 19 日发布的设计咨询提醒
01/19/2015 | (赛灵思答复记录 63110) | 面向 7 系列 GTH 收发器向导的设计咨询:在 Vivado 2013.4 升级到 2014.4 后,经调整后 DFE 被错误设置为 HOLD。 |
2014 年 11 月 10 日发布的设计咨询提醒
11/10/2014 | (赛灵思答复记录 62631) | 面向 Vivado 2014.3 的设计咨询 - 针对 7 系列和 UltraScale FPGA 的编程 eFUSE 寄存器操作失败 | [SECURITY] |
2014 年 9 月 22 日发布的设计咨询提醒
09/29/2014 | (赛灵思答复记录 61875) | 面向基于 QPLL 的 7 系列 FPGA GTX/GTH 设计的设计咨询:配置完成后最少 500ns 的时间内不能启用 QPLLPD。 |
2014 年 9 月 1 日发布的设计咨询提醒
09/01/2014 | (赛灵思答复记录 61748) | 面向 Vivado Power/XPE 的设计咨询 - GTH - LPM/DFE 模式在 XPE 中 MGTAVcc 电流低报。 |
2014 年 6 月 16 日发布的设计咨询提醒
06/16/2014 | (赛灵思答复记录 60845) | 面向 MIG 7 系列 RLDRAM3 的设计咨询 - 针对综合和实现的 SIM_BYPASS_INIT_CAL 被错误设置为“FAST” |
2014 年 5 月 26 日发布的设计咨询提醒
05/26/2014 | (赛灵思答复记录 60356) | 面向 7 系列 FPGA 收发器向导 v3.2 或更低版本的设计咨询 - 必需 XDC 约束更新 |
05/26/2014 | (赛灵思答复记录 60489) | 面向 7 系列 FPGA 收发器向导 v3.2 或更低版本的设计咨询:GTH/GTP Production RX 复位顺序停滞 |
05/26/2014 | (赛灵思答复记录 45360) | 面向 Kintex-7 和 Virtex-7 FPGA GTX 收发器的设计咨询 - 更新对应 SATA Gen 2/Gen 3 的 RXCDR_CFG 设置,PMA_RSV 更新为 6.6 Gbps |
2014 年 1 月 20 日发布的设计咨询提醒
01/20/2014 | (赛灵思答复记录 59035) | 面向 7 系列 FPGA GTX/GTH 收发器的设计咨询 - QPLL 不支持 PCIe Gen1/Gen2 |
2013 年 11 月 25 日发布的设计咨询提醒
11/25/2013 | (赛灵思答复记录 58244) | 面向 7 系列 FPGA GTX 收发器的设计咨询 - DFE 模式下的 RXDFEXYDEN 端口更新 |
11/25/2013 | (赛灵思答复记录 45360) | 面向 Kintex-7 和 Virtex-7 FPGA GTX 通用 ES 收发器的设计咨询更新:新增对应用户指南 UG476 中有关 RX_DFE_KL_CFG2 设置的引用 |
2013 年 10 月 23 日发布的设计咨询提醒
10/23/2013 | (赛灵思答复记录 51554) | 面向 Aurora 64B66B v8.1 或更早版本的设计咨询 - 内核初始化在连续 RESET 和 PMA_INIT 输入上不一致 |
2013 年 9 月 16 日发布的设计咨询提醒
09/16/2013 | (赛灵思答复记录 57193) | 面向 Artix-7、Kintex-7、Virtex-7、Zynq-7000 封装的设计咨询 - 7 系列热阻值(Theta-JA、Theta-JB 和 Theta-JC)更新,提供更精确的值,许多值有大幅更改 |
2013 年 8 月 5 日发布的设计咨询提醒
08/05/2013 | (赛灵思答复记录 55009) | 面向 7 系列 FPGA GTX/GTH/GTP 收发器的设计咨询更新 - TX 同步控制器在缓冲旁路模式下的相位对齐变更,包含 IP 答复记录的链接 |
2013 年 7 月 29 日发布的设计咨询提醒
07/29/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询:QPLL_CFG、QPLL_LOCK_CFG 和 QPLL_LOCK_CFG 属性更新 |
07/29/2013 | (赛灵思答复记录 56332) | 面向 Virtex-7 GTH 的设计咨询 - 量产芯片的 QPLL 属性更新:QPLL_CFG、QPLL_LOCK_CFG 和 COMMON_CFG 属性更新 |
2013 年 5 月 20 日发布的设计咨询提醒
05/16/2013 | (赛灵思答复记录 55009) | 面向 7 系列 FPGA GTX/GTH/GTP 收发器的设计咨询更新 - TX 同步控制器在缓冲旁路模式下的相位对齐变更,包含 IP 答复记录的链接 |
2013 年 5 月 13 日发布的设计咨询提醒
05/13/2013 | (赛灵思答复记录 55366) | 面向 7 系列 FPGA GTX/GTH/GTP 收发器的设计咨询 - 收发器向导设置非最佳的 RX 端接使用模式 |
2013 年 4 月 15 日发布的设计咨询提醒
04/12/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询:将 GTHE2_COMMON/BIAS_CFG 使用模式更新为包含时钟随路,并新增 RX 复位顺序的 TX 同步控制器部分 |
2013 年 4 月 3 日发布的设计咨询提醒
04/03/2013 | (赛灵思答复记录 55009) | 面向 7 系列 FPGA GTX/GTH/GTP 收发器的设计咨询 - 缓冲旁路模式下的 TX 同步控制器相位对齐变更 |
03/26/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询:RX_DFE_KL_CFG 设置更新 |
04/03/2013 | (赛灵思答复记录 50906) | 面向量产 (Production) Kintex-7 325T、410T、420T 和 Virtex-7 485XT、690XT 的设计咨询 - GES 与 Production 器件之间的比特流兼容性要求:7V690T 量产器件更新 |
2013 年 3 月 19 日发布的设计咨询提醒
03/07/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询:LPM 端口设置更新为调整模式,QPLL_CFG 设置从“line rate”更改为 QPLL 频率 |
2013 年 2 月 25 日发布的设计咨询提醒
02/21/2013 | (赛灵思答复记录 53779) | 面向 Virtex-7 FPGA GTH 量产 (Production) 收发器 RX 复位顺序要求的设计咨询;已更新以反映正确的 GTH 模式组合,其中含全新复位要求 |
2013 年 2 月 18 日发布的设计咨询提醒
02/15/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询:新增对应 PCIe Gen3 的 RXCDR_CFG 设置,DFE 端口设置更新为调整模式 |
2013 年 2 月 11 日发布的设计咨询提醒
02/04/2013 | (赛灵思答复记录 47128) | 面向 Virtex-7 FPGA GTH 收发器的设计咨询 - 面向初始工程样品 (ES) 芯片的属性更新、问题及变通方法;新增 PCS_RSVD_ATTR[8] 和注释 |
2013 年 2 月 4 日发布的设计咨询提醒
2013 年 1 月 21 日发布的设计咨询提醒
01/17/2013 | (赛灵思答复记录 53740) | 面向 7 系列赛灵思 PCI Express 核的设计咨询更新 - 低温下 TXOUTCLK 上无时钟输出。 |
2013 年 1 月 14 日发布的设计咨询提醒
01/09/2013 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询提醒:更新 BIAS_CFG、QPLL_CFG 设置并在表中新增 QPLL_CLKOUT_CFG。 |
2012 年 12 月 18 日发布的设计咨询提醒
12/13/2012 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 通用 ES 收发器的设计咨询更新:新增对应 SATA SSC 的 RXCDR_CFG 设置,并新增有关不使用 OOB 时的 RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE 的注释。 |
12/13/2012 | (赛灵思答复记录 45360) | 更新有关 Kintex-7 和 Virtex-7 FPGA GTX 通用 ES 收发器的设计咨询: 为 SATA SSC 新增了 RXCDR_CFG 设置,并新增了在不使用 OOB 时有关 RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE 的注释。 |
2012 年 11 月 13 日发布的设计咨询提醒
2012 年 11 月 5 日发布的设计咨询提醒
10/31/2012 | (赛灵思答复记录 50617) | 面向 Kintex-7 和 Virtex-7 FPGA 量产 GTX 收发器的设计咨询更新,包含对应特定器件的引用;更新比特流兼容性部分 |
10/25/2012 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 收发器的设计咨询更新 - 面向通用工程样品 (ES) 芯片的属性更新、问题及变通方法;新增对应 8B/10B 的 RXCDR_CFG 值 |
2012 年 10 月 18 日发布的设计咨询提醒
10/17/2012 | (赛灵思答复记录 51625) | 面向 Virtex-7 FPGA GTH 收发器的设计咨询 - 面向通用工程样品 (ES) 芯片的属性更新、问题及变通方法 |
10/17/2012 | (赛灵思答复记录 51884) | 面向 Kintex-7 和 Virtex-7 FPGA GTX 量产芯片的设计咨询 - CDR 属性更新 |
10/17/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 FPGA GTH 收发器的设计咨询更新 - 面向初始工程样品 (ES) 芯片的属性更新、问题及变通方法;新增 ACJTAG 使用模式 |
2012 年 9 月 10 日发布的设计咨询提醒
09/10/2012 | (赛灵思答复记录 51580) | 面向 14.1/14.2 时序分析 7 系列 FPGA 的设计咨询 - 针对块 RAM (BRAM) 或 FIFO 组件的时钟到达时间不正确,无法进行 PERIOD 约束分析 |
答复记录已升级至设计咨询
09/10/2012 | (赛灵思答复记录 45781) | 面向 7 系列 XADC 的设计咨询 - 使用 XADCEnhancedLinearity BitGen 选项 |
2012 年 8 月 20 日发布的设计咨询提醒
08/20/2012 | (赛灵思答复记录 51296) | 设计咨询 - ISE 14.2 和 Vivado 2012.2 Design Suite 版本中 7 系列封装飞行时间 (Package Flight Time) 的变更 |
08/17/2012 | (赛灵思答复记录 50906) | 面向量产 Kintex-7 325T、410T 和 Virtex-7 485XT 的设计咨询 - GES 与 Production 器件之间的比特流兼容性要求 |
08/17/2012 | (赛灵思答复记录 47443) | 面向 Virtex-7 GTH 收发器上电/下电的设计咨询更新(VMGTAVTT 更新)其它电流汲取值 |
2012 年 8 月 13 日发布的设计咨询提醒
08/10/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 GTH 初始 ES 收发器的设计咨询更新:在 GTHE2_COMMON/BIAS_CFG 部分中提供 GTHE2_COMMON 例化示例,并新增针对 ISE 14.2/Vivado 2012.2 的部分常规引用。 |
2012 年 7 月 30 日发布的设计咨询提醒
07/27/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 GTH 初始 ES 收发器的设计咨询更新,即 GTH 电阻校准正确且无需变通方法。 |
2012 年 7 月 25 日发布的设计咨询提醒
07/19/2012 | (赛灵思答复记录 47443) | 面向 Virtex-7 GTH 收发器上电/下电的设计咨询更新,含电流汲取持续时间信息、同步上电信息及其它 FAQ。 |
07/19/2012 | (赛灵思答复记录 47817) | 面向 Kintex-7/Virtex-7 GTX 收发器上电/下电的设计咨询更新,含遵循建议顺序情况下的附加电流汲取信息、有关电流汲取持续时间的信息、同步上电信息及其它 FAQ。 |
07/19/2012 | (赛灵思答复记录 45360) | 面向 Kintex-7 和 Virtex-7 FPGA GTX 通用 ES 收发器的设计咨询更新(含 RX_DFE_XYD_CFG 值)。 |
2012 年 7 月 16 日发布的设计咨询提醒
07/12/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 GTH 初始 ES 收发器的设计咨询更新,含 QPLL_CFG 和 QPLL_LOCK_CFG 更新值以及“GTH 收发器链接余量减少”部分。 |
2012 年 7 月 2 日发布的设计咨询提醒
06/28/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 GTH 初始 ES 收发器的设计咨询更新,在属性和端口部分中包含最新 PMA_RSV2、RX_BIAS_CFG 和 RXDFEXYDEN 值。 |
06/28/2012 | (赛灵思答复记录 45360) | 面向 Kintex-7 和 Virtex-7 FPGA GTX 收发器的设计咨询 - 面向通用工程样品 (ES) 芯片的属性更新、问题及变通方法。 |
2012 年 6 月 11 日发布的设计咨询提醒
2012 年 5 月 28 日发布的设计咨询提醒
05/24/2012 | (赛灵思答复记录 47128) | 设计咨询更新,包含 GTHE2_COMMON 和终端使用模式、初始 ES 勘误表项部分,并更新电阻校准部分。 |
2012 年 5 月 15 日发布的设计咨询提醒
05/14/2012 | (赛灵思答复记录 47128) | 设计咨询标题更新为“Virtex-7 FPGA GTH 收发器 - 面向初始工程样品 (ES) 芯片的属性更新、问题及变通方法”,包含“电阻校准”部分,并更新了 BIAS_CFG 设置 |
2012 年 5 月 8 日发布的设计咨询提醒
05/03/2012 | (赛灵思答复记录 47128) | 面向 Virtex-7 FPGA GTH 收发器的设计咨询 - 面向初始工程样品 (ES) 芯片的属性更新和使用模式 |
2012 年 4 月 30 日发布的设计咨询提醒
2012 年 1 月 16 日发布的设计咨询提醒
01/10/2012 | (赛灵思答复记录 45633) | 面向 7 系列 MIG DDR3/DDR2 的设计咨询 - 针对 CKE 和 ODT 的管脚布局更新;现有 UCF 必须验证 |
2011 年 11 月 21 日发布的设计咨询提醒
2011 年 7 月 6 日发布的设计咨询提醒
07/06/2011 | (赛灵思答复记录 42615) | 面向 7 系列 FPGA 收发器的设计咨询 - ISE 13.2 设计咨询中的 GTX 端口名称变更 |