AR# 46426

ChipScope Pro - Inserting ChipScope cores in the PlanAhead tool generates unconnected ports

描述


Inserting ChipScope cores in the PlanAhead tool generates unconnected ports in the 13.3 and 13.4 design tools. BitGen displays DRC errors similar to the following when this occurs:

"ERROR:PhysDesignRules:10 - The network <xxxx_cs_ila_0_0> is completely unrouted."

解决方案

To avoid this issue, add KEEP attributes to the nets reported in the BitGen DRC, and run again through XST and implementation.
AR# 46426
日期 05/07/2012
状态 Active
Type 综合文章
Tools