This answer record provides guidance on creating a design for the7 series FPGA.
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
When designing for 7 series FPGAs, review the Application Notes and Intellectual Property (IP) to determine if there are any which can be used for the application you are targeting.
7 SeriesFPGA Application Notes:http://www.xilinx.com/support/documentation/7_series_application_notes.htm
7 SeriesFPGA IP:http://www.xilinx.com/ipcenter/index.htm
For design areas not covered by IP orApplication Notes, the following answer records provide guidance on how to move forward with a 7 series FPGA design:
(Xilinx Answer 46493) - Designing clocking structures in7 series FPGAs
(Xilinx Answer 46506) - Designing configurable logic structures in7 series FPGAs
(Xilinx Answer 46513) - Designing block RAM and FIFO structures in7 series FPGAs
(Xilinx Answer 46517) - Designing for I/O, PCIe, EMAC, DSP, andXADC in7 series FPGAs
Review the 7 Series FPGA User Guides (Xilinx Answer 46436). If migrating a design from a previous FPGA architecture to 7 series FPGAs, review the 7 Series FPGAs Migration Methodology Guide.
For special considerations when targeting large 7 series FPGAs, especially those with Stacked Silicon Interconnect (SSI) Technology, review the Large FPGA Methodology Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ug872_largefpga.pdf