This answer record discusses how shift register look-up tables (SRLs) can be used to help conserve resources in fabric.
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
The SRL primitive can be utilized to reduce resources used in a design. Instead of implementing a shift register using a series of flip-flops, you can implement a shift register in the dedicated performance optimized SRL blocks in fabric. However, in order to utilize an SRL in your design, you must be careful how you use resets.
Resets should not be used on shift registers in your design as this requires additional logic around the SRL block which reduces performance and increases the amount of logic needed to implement the shift register.
For more information on using SRLs in your design, see the section on SRLs in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231): http://www.xilinx.com/support/documentation/white_papers/wp231.pdf