AR# 46512: 7 Series FPGA Design Assistant - Using optimization features from third-party synthesis tools
7 Series FPGA Design Assistant - Using optimization features from third-party synthesis tools
The following Answer Record discusses how optimization features can be used from third-party synthesis tools to help optimize your design.
NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
Some third-party synthesis tools such as Synplify Pro have optimization features that can help to improve performance with your design. For more information on synthesis tool settings that should be utilized, see the HDL Coding Practices to Accelerate Design Performance White Paper (WP231): http://www.xilinx.com/support/documentation/white_papers/wp231.pdf
The following is a list of sections in White Paper 231 that specifically mention the different synthesis tool settings:
"Maximize Block RAM Performance"
"Use of I/O Registers"
"Replicate Registers with High-Fanout"
"Nested If-Then-Else, Case Statements, and Combinatorial For-Loops"