We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46515

7 Series FPGA Design Assistant - How to infer the use of Block RAM and FIFO primitives in your HDL code


The following Answer Record points you to information on how to infer block RAM and FIFO primitives in your HDL code.

Note: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370)

The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices.

Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


Block RAMs and FIFOs can be inferred if implemented correctly in your HDL code.

The XST User Guide (UG627) discusses in detail how you need to code in order to infer a block RAM or FIFO in your design:


In addition, the HDL Coding Practices to Accelerate Design Performance White Paper (WP231) provides additional information on coding techniques that can be used to optimize performance of Block RAM in your design.

Refer to the "Maximize Block RAM performance" section:




Answer Number 问答标题 问题版本 已解决问题的版本
46517 7 Series FPGA Design Assistant - Designing for I/O, PCIe, EMAC, DSP, and XADC in 7 Series FPGAs N/A N/A
AR# 46515
日期 11/15/2017
状态 Active
Type 解决方案中心