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AR# 46535

KC705 User Guide (UG810) - GPIO_DIP_SW0 pinout incorrect in Table 1-24

Description

In Table 1-24 of the KC705 Evaluation Board for the Kintex-7 FPGA User Guide v1.0 (UG810), the FPGA pin for GPIO_DIP_SW0 is listed as AB25. However, the schematic and the UCF for the KC705 lists the FPGA pin for GPIO_DIP_SW0 as Y29.

Which is the correct FPGA pin for GPIO_DIP_SW0?

解决方案

The schematic and the UCF are correct; GPIO_DIP_SW0 is connected to FPGA pin Y29 on the Kintex-7 device.

Table 1-26 of the KC705 Evaluation Board for the Kintex-7 FPGA User Guide v1.1 (UG810) has been updated to reflect the correct FPGA connection.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 46535
创建日期 02/27/2012
Last Updated 01/10/2014
状态 Active
Type 综合文章
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit