AR# 46554


Vivado Timing - write_xdc expands all_registers command


I have the following constraint in my design:

set_false_path -from [get_ports tss_clk] -to [all_registers -edge_triggered]

When I issue a write_xdc for this design, it will expand all_registers so that all cells are now defined. This is very messy.


The workaround is to manually re-write the XDC file.
AR# 46554
日期 08/07/2013
状态 Active
Type 已知问题
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