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AR# 46563

AXI Bridge for PCI Express - Selecting 128-bit Interface Width for x8 Gen 1 or x4 Gen 2 results in ERROR:HDLCompiler:410 error

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When targeting a 128-bit AXI interfacing using a x8 Gen 1 or x4 Gen 2 configuration, the following errors occur:

ERROR:HDLCompiler:410 - "/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 541: Expression has 64 elements ; expected 128
ERROR:HDLCompiler:410 - "/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_read_req_tlp.vhd" Line 511: Expression has 64 elements ; expected 128
ERROR:HDLCompiler:410 - "/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_read_cpl_tlp.vhd" Line 511: Expression has16 elements ; expected 32

解决方案

This zip file contains three files needed to fix this problem:

http://www.xilinx.com/txpatches/pub/applications/pci/ar46563.zip

To resolve this issue, follow these instructions:

  1. Make the IP local; to make the IP local:
    1. Find the IP in the System Assembly view and right-click the IP.
    2. Select Make This IP Local.
  2. After the IP is local, go to the "/pcores/axi_pcie_v1_02_a_axi_pcie_mm_s_v1_02_a/hdl/vhdl" directory.
  3. Copy the three files from the zip into this directory, replacing the existing files.

Revision History
02/27/2012 - Initial release

NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46563
创建日期 02/28/2012
Last Updated 05/20/2012
状态 Active
Type 已知问题
IP
  • AXI PCI Express (PCIe)