If a large read request is received from the AXI interface which is split into smaller memory read TLPs to be sent to the PCIe system, it is possible that a completion timeout can be triggered. This happens if the first Memory Read TLP is sent, and the following reads are stalled due to lack of credits from the link partner. The completion timeout logic starts counting based on the AXI read request instead of the individual TLP request sent to the PCIe system. In this scenario the timer may expire before the completions for all memory reads are returned, due to the subsequent reads being stalled due to lack of credits.
This problem is only likely to occur if the link partner is not returning sufficient credits to allow the non-posted packets to be transmitted. A potential workaround for this issue is to not issue any AXI read requests to the bridge larger than the Maximum Read Request size programmed in to the PCI Express device control register.
A fix for this issue is not yet available, but is being investigated. If this issue is a concern, please open a case with Xilinx support and refer to this answer record.
Revision History 03/05/2012 - Initial Release
NOTE: The "Version Found" column lists the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.