The attached reference design is an example to show the flow to integrate HDL generated with the AutoESL tool from a C++ source into a System Generator design using the Blackbox flow.
The System Generator design is the demo design Costas Loop. A simple complex multiplier module has been written in C and synthesized with AutoESL with simple interfaces and zero latency. In this case, the design cannot afford to have any sample delay in the path.
The System Generator design incorporates the HDL modules using the HDL Blackbox flow.
Design Languages (HDL/SW): System Generator, AutoESL
Design Reference Document:
One ZIP file is included, and within the ZIP file under the 'costas_loop' directory there is an AutoESL project and a System Generator project. The System Generator project includes the model and a config.m file (cmplx_mult_top_config.m) that links the blockbox component in System Generator to the VHDL source.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 47431 | Xilinx Vivado HLS Solution Center - Design Assistant | N/A | N/A |