When the AXI Bridge for PCI Express is configured as x4 gen2 or x8 gen1, incoming memory read request TLPs will be dropped when the length field of the TLP is zero. x4 gen2 and x8 gen1 both use the 128-bit AXI data width interface, which is why this is only seen in only those configurations.
If a system issues memory read requests with a length of zero, a completion timeout will occur in the system. To work around this issue, make sure to have all requests have a payload in all memory read requests.
A fix for this issue is not yet available, but is being investigated. If this issue is a concern please open a case with Xilinx support and refer to this answer record.
03/05/2012 - Initial Release
NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.