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AR# 46646

AXI Bridge for PCI Express - In Root Port mode, memory read completion can be lost if Memory Read TLPs and Configuration TLPs are outstanding at the same time

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

The AXI MM Bridge for PCIe is designed to hold off sending Memory Read TLPs when a configuration TLP is sent. This is done so that the bridge can safely assume the returned completion is for the configuration request, which makes routing the completions less timing intensive. However, under some conditions, if configurationrequest TLPs are pending and read request is being received from the AXI interface, a memory read TLP is incorrectly transmitted while the configuration completion is still outstanding. While this is compliant from a PCI Express perspective, the bridge is not designed to handle this scenario.

The result is that the completions with data for the memory read request will be routed incorrectly and purged internally in the AXI MM bridge, and not returned to the AXI interface.

解决方案

This issue is fixed in v1.03a, which will be released in ISE 14.1 software.Prior to ISE 14.1 release, if this issue is a concern, please open a case with Xilinx support and refer to this answer record. To work around this issue, do not send read request from the AXI side until all configuration requests to enumerate and configure the link partner device are completed.

Revision History
03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46646
创建日期 03/02/2012
Last Updated 05/20/2012
状态 Active
Type 已知问题
IP
  • AXI PCI Express (PCIe)