A zero-length write transaction on the AXI Slave port of the AXI Bridge for PCI Express will cause the AXI interface to stall by deasserting either a wread or wready of the Write Address or Write Data Channel, respectively.
To work around this issue, avoid mastering on the AXI Slave Write Channel with a zero-length write transaction.
A fix for this issue is not yet available, but is being investigated. If this issue is a concern, please open a case with Xilinx support and refer to this answer record.
03/05/2012 - Initial Release
NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.