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  3. AR# 46676: MIG 7 Series v1.4 RLDRAM II - Synthesis fails when DEBUG_PORT is turned OFF in RTL

AR# 46676

MIG 7 Series v1.4 RLDRAM II - Synthesis fails when DEBUG_PORT is turned OFF in RTL

Description

MIG 7 Series v1.4 RLDRAM II designs fail during synthesis when the design is generated with the "Debug Signals for Memory Controller" ON in the MIG GUI, but then manually turned off in the top-level RTL.

解决方案

When the DEBUG_PORT is turned "OFF" in the top-level module example_top.v or <user_design>.v, the following errors occur:

XST:

ERROR:HDLCompiler:1401 - "C:\Users\vsrunga\Desktop\MIG_RLDRAM_Debug_ON\mig_7series_v1_4\example_design\rtl\example_top.v" Line 857: Signal dbg_win_current_byte[3] in unit example_top is connected to following multiple drivers:

ERROR:HDLCompiler:1379 - "C:\Users\vsrunga\Desktop\MIG_RLDRAM_Debug_ON\mig_7series_v1_4\example_design\rtl\example_top.v" Line 896: Driver 0: output signal of instance Ground

ERROR:HDLCompiler:1379 - "C:\Users\vsrunga\Desktop\MIG_RLDRAM_Debug_ON\mig_7series_v1_4\example_design\rtl\example_top.v" Line 857: Driver 1: u_chk_win_top/win_current_byte[3] driven by output signal win_current_byte[3] of instance Flip-flop

ERROR:HDLCompiler:1379 - "C:\Users\vsrunga\Desktop\MIG_RLDRAM_Debug_ON\mig_7series_v1_4\example_design\rtl\example_top.v" Line 893: Driver 0: output signal of instance Ground

Synplify Pro

@E: CG596 :"/home/vsrunga/MIG_Work/MIG_RLDRAM_Debug_ON/mig_7series_v1_4/user_design/rtl/phy/qdr_rld_byte_lane.v":371:8:371:25|Parameter PHASEREFCLK_PERIOD cannot be found in module PHASER_IN.

@END

This is because debug ports are driven by chk_win_top module and also by the generate statement leading to multiple drivers for dbg nets. As a temporary workaround, the user can comment the generate statement in the example_top.v (lines 887 -898) and rerun the design, or they can regenerate the design from scratch with the "Debug Signals for Memory Controllers" OFF.

generate

if (DEBUG_PORT != "ON") begin: gen_chk_win_off

assign dbg_win_left_ram_out = 'b0;
assign dbg_win_right_ram_out = 'b0;
assign dbg_win_active = 1'b0;
assign dbg_win_clr_error = 1'b0;
assign dbg_win_inc = 1'b0;
assign dbg_win_dec = 1'b0;
assign dbg_win_current_bit = 'b0;
assign dbg_win_current_byte = 'b0;

end

endgenerate

This is currently scheduled to be fixed in the 14.1 release.
AR# 46676
日期 10/16/2012
状态 Active
Type 已知问题
器件
  • Kintex-7
Tools
  • ISE Design Suite - 13.4
IP
  • MIG 7 Series