AR# 4673: SYNPLIFY: How to change the initialization state of a flip-flop using INIT?
SYNPLIFY: How to change the initialization state of a flip-flop using INIT?
Keywords: INIT, Synplify, Verilog, VHDL
General Description: How to change the initialization state of a FF?
For XC4000 devices, when a preset or clear pin on a flip-flop is connected to an active signal, the state of that signal controls the startup state of the flip-flop. For example, if you connect an active signal to the preset pin, the flip-flop starts up in the preset state. If you do not connect the clear or preset pin, the default startup state is a clear state. To change the default to preset, assign an INIT=S attribute to the flip-flop.
By default, all registers in an XC9500 device are initialized to zero when powered up. The registers in XC9000 macrocells have both asynchronous clear and asynchronous preset controls available. So, the initial power-on states of CPLD macrocell registers can be selected regardless of whether the register is asynchronously cleared (INIT=R) or preset (INIT=S) during operation.