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AR# 46740

Spartan-6 FPGA Design Assistant - Designing block RAM in Spartan-6 FPGAs


This Answer Record provides information on how to use the block RAM in the Spartan-6 FPGA fabric.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


The built-in block RAM primitive in the Spartan-6 FPGA can be used to implement RAMs, ROMs, and FIFO blocks for a design.The block RAMis optimized for performance and allows you to implementa RAM, ROM, or FIFO block in a design without requiring large amounts of fabric resources from slice logic.

The Spartan-6 FPGABlock RAM ResourcesUser Guide (UG383)provides additional details on the block RAM. It is recommended that you read through the user guide to familiarize yourself with its use and howit can be used in your design:

In addition, the following Answer Recordsare useful in providing details on different ways to implement block RAM blocks in your code:
(Xilinx Answer 46748) - How to infer the use of Block RAM primitive in your HDL code
(Xilinx Answer 46747) - Using block RAM CORE Generator and to setup the block for use in HDL code



Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A


AR# 46740
创建日期 03/27/2012
Last Updated 12/15/2012
状态 Active
Type 综合文章
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q