Would Vivado Synthesis be able to infer tristate logic in a lower level module when flatten_hierarchy is set to none?
When the -flatten_hierarchy switch is set to "none," it is not recommended to have tristate at lower level.
In case of a design containing tristate logic, setting flatten_hierarchy to "none" does not actually force the design to preserve hierarchy.
Vivado synthesis automatically flattens the hierarchy before the I/O insertion stage while trying to infer a tristate primitive for a tristate logic in a lower level module and then rebuild the hierarchy.
The workaround would be either setting -flatten_hierarchy to "full" or "rebuilt" or move the tristate logic to top level in the HDL code.