AR# 46745


Spartan-6 FPGA Design Assistant - Designing configurable logic structures in Spartan-6 FPGAs


This Answer Record provides guidance and information on what you should know about FPGA fabric configuration and setup.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


When coding for a Spartan-6 FPGA design, you should follow the coding guidelines shown in the language templates and also follow the recommendations for coding practices discussed in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231):

Follow the recommendations mentioned in this White Paper, so that the software tools optimally utilize the FPGA fabric. You can also refer to the following Answer Records for more information on coding methods that can help optimize performance and reduce the amount of logic used in a design:

(Xilinx Answer 46752) - Utilizing distributed memory in fabric
(Xilinx Answer 46738) - Setting logic controls in the fabric
(Xilinx Answer 46765) - Using SRLs to conserve resources
(Xilinx Answer 46766) - Using optimization features from third-party synthesis tools

In addition, the Spartan-6 FPGA Configurable Logic Block User Guide (UG384) describes the primitives and blocksin more detail so that you have a better understanding of how the Spartan-6 FPGA fabric can work for you in a design:



Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A


AR# 46745
日期 12/15/2012
状态 Active
Type 综合文章
People Also Viewed