AR# 46748: Spartan-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code
Spartan-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code
The following Answer Record points you to information on how to infer block RAM and FIFO primitives in your HDL code.
NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.
Specifically, the "RAMs and ROMs Hardware Description Language (HDL) Coding Techniques" section provides details on how to infer RAMs and ROMs built using block RAM in your design.
In addition, theHDL Coding Practices to Accelerate Design Performance White Paper (WP231)provides additional information on coding techniques that can be used to optimize performance of Block RAM in your design.Refer tothe "Maximize Block RAM performance" section: http://www.xilinx.com/support/documentation/white_papers/wp231.pdf