UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46758

13.4 EDK - Can I use CCLK for configuring my FPGA instead of the JTAGCLK in SDK?

Description

Can I use CCLK for configuring my FPGA instead of the JTAGCLK in SDK?

解决方案

Yes, this option can be set in the bitgen options in XPS (in the Project Tab view), or set in the etc/bitgen.ut file. SDK can configure the FPGA using either the JTAG clock (JTAGCLK), or another (generally tied to flash, CCLK) clock.
AR# 46758
创建日期 11/13/2012
Last Updated 11/14/2012
状态 Active
Type 综合文章
Tools
  • EDK - 13.4