AR# 46761


7 Series FPGA Design Assistant - Design behaves differently in hardware


The following answer record has some suggestions that can help resolve issues with designs not behaving as expected in hardware.

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


Below are somesuggestions that can help debug issues where a design behaves differently in hardware than expected

  • First, run a behavioral simulation of your design and verify functionality in the behavioral simulation. If the behavioral simulation does not work properly, there is a logic issue in your design
  • Run a post-PAR timing simulation of the design. If the design does not work in a timing simulation, part of your design may not be properly constrained. Please refer to the Xilinx Timing Solution Center for more information on timing (Xilinx Answer 40832)
  • Place ChipScope in your design and use it to probe parts of the design to help narrow down where the failure is occurring in the design. For more information on the ChipScope tool, please visit the ChipScope product page (

If you still cannot resolve any implementation related fabric issues, please open up a case with Xilinx Technical Support (



Answer Number 问答标题 问题版本 已解决问题的版本
46759 7 Series FPGA Design Assistant - Troubleshooting common fabric problems N/A N/A
40832 Xilinx 时序分析解决方案中心 N/A N/A
AR# 46761
日期 12/15/2012
状态 Active
Type 综合文章
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