The following answer record will help guide you to solutions to issues relating to the 7 Series Block RAM and FIFO.
NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
Please refer to the suggestions below for suggestions that can be used to help debug issues relating to the 7 Series Block RAM or FIFO:
- Refer to the 7 Series Memory Resources User Guide and verify that your usage of the Block RAM or FIFO block is a legal configuration (http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf)
- Run a behavioral simulation of the design and verify proper functionality of the Block RAM or FIFO.
- Run a post-PAR timing simulation and verify proper functionality. If a failure occurs here, your design may not be properly constrained.
- Also check the timing report to ensure all control signals are properly constrained and synchronous. Check the Xilinx Timing Solution Center (Xilinx Answer 40832) for more information on timing in a Xilinx FPGA design.
- Insert ChipScopeanalyzerinto your design and probe all the ports of the FIFO or Block RAM. ChipScope analyzer can be used to probe parts of your design in fabric and view these signals in real time in hardware. For more information on ChipScope tool, please visit the ChipScope product page athttp://www.xilinx.com/tools/cspro.htm
If you still have an issue with the Block Ram or FIFO in your design, please open up a webcase with Xilinx Technical Support athttp://www.xilinx.com/support/clearexpress/websupport.htm.