Shift Registers in Spartan-6 FPGA are most optimized for implementation in the SLICEMs. A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data anywhere from one to 32 clock cycles. The shiftinD and shiftoutQ lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM can thus be cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers across more than one SLICEM.
Applications requiring delay or latency compensation use these shift registers to develop efficient designs. Shift registers are also useful in synchronous FIFO and content addressable memory (CAM) designs.
Resets should not be used on shift registers in your design, as this requires additional logic around the SLICEM SRLwhich can reduce performance and increases the amount of logic needed to implement the shift register.
For more information on using SRLs in your design, see the section on SRLs in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231):
Also reference the Spartan-6 FPGA CLB User Guide (UG384):